diff options
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/extract.cc | 4 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 8 |
2 files changed, 6 insertions, 6 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 994ef8f2a..ff99040e1 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -42,7 +42,7 @@ public: { } - bool compareAttributes(const std::set<RTLIL::IdString> &attr, const std::map<RTLIL::IdString, RTLIL::Const> &needleAttr, const std::map<RTLIL::IdString, RTLIL::Const> &haystackAttr) + bool compareAttributes(const std::set<RTLIL::IdString> &attr, const dict<RTLIL::IdString, RTLIL::Const> &needleAttr, const dict<RTLIL::IdString, RTLIL::Const> &haystackAttr) { for (auto &it : attr) { size_t nc = needleAttr.count(it), hc = haystackAttr.count(it); @@ -123,7 +123,7 @@ public: { RTLIL::Wire *lastNeedleWire = NULL; RTLIL::Wire *lastHaystackWire = NULL; - std::map<RTLIL::IdString, RTLIL::Const> emptyAttr; + dict<RTLIL::IdString, RTLIL::Const> emptyAttr; for (auto &conn : needleCell->connections()) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 04d345d31..94dd4d42c 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -341,7 +341,7 @@ struct TechmapWorker { RTLIL::IdString derived_name = tpl_name; RTLIL::Module *tpl = map->modules_[tpl_name]; - std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters; + std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end()); if (tpl->get_bool_attribute("\\blackbox")) continue; @@ -529,7 +529,7 @@ struct TechmapWorker tpl = techmap_cache[key]; } else { if (cell->parameters.size() != 0) { - derived_name = tpl->derive(map, parameters); + derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end())); tpl = map->module(derived_name); log_continue = true; } @@ -975,7 +975,7 @@ struct TechmapPass : public Pass { Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend); } - std::map<RTLIL::IdString, RTLIL::Module*> modules_new; + dict<RTLIL::IdString, RTLIL::Module*> modules_new; for (auto &it : map->modules_) { if (it.first.substr(0, 2) == "\\$") it.second->name = it.first.substr(1); @@ -1072,7 +1072,7 @@ struct FlattenPass : public Pass { log("No more expansions possible.\n"); if (top_mod != NULL) { - std::map<RTLIL::IdString, RTLIL::Module*> new_modules; + dict<RTLIL::IdString, RTLIL::Module*> new_modules; for (auto mod : design->modules()) if (mod == top_mod || mod->get_bool_attribute("\\blackbox")) { new_modules[mod->name] = mod; |