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-rw-r--r--passes/tests/test_abcloop.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc
index 894610e2b..2d80e66e4 100644
--- a/passes/tests/test_abcloop.cc
+++ b/passes/tests/test_abcloop.cc
@@ -132,7 +132,7 @@ static void test_abcloop()
SatGen satgen(ez.get(), &sigmap);
for (auto c : module->cells()) {
- bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
+ bool ok = satgen.importCell(c);
log_assert(ok);
}
@@ -182,7 +182,7 @@ static void test_abcloop()
SatGen satgen(ez.get(), &sigmap);
for (auto c : module->cells()) {
- bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
+ bool ok = satgen.importCell(c);
log_assert(ok);
}
@@ -244,7 +244,7 @@ static void test_abcloop()
struct TestAbcloopPass : public Pass {
TestAbcloopPass() : Pass("test_abcloop", "automatically test handling of loops in abc command") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -259,7 +259,7 @@ struct TestAbcloopPass : public Pass {
log(" use this value as rng seed value (default = unix time).\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design*) override
{
int num_iter = 100;
xorshift32_state = 0;