diff options
Diffstat (limited to 'passes/tests')
| -rw-r--r-- | passes/tests/test_autotb.cc | 2 | ||||
| -rw-r--r-- | passes/tests/test_cell.cc | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 659f0bb69..bb516fca9 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -310,7 +310,7 @@ struct TestAutotbBackend : public Backend { log("\n"); log(" test_autotb [options] [filename]\n"); log("\n"); - log("Automatically create primitive verilog test benches for all modules in the\n"); + log("Automatically create primitive Verilog test benches for all modules in the\n"); log("design. The generated testbenches toggle the input pins of the module in\n"); log("a semi-random manner and dumps the resulting output signals.\n"); log("\n"); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index bd3749b71..abac62231 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -556,7 +556,7 @@ struct TestCellPass : public Pass { log(" print additional debug information to the console\n"); log("\n"); log(" -vlog {filename}\n"); - log(" create a verilog test bench to test simlib and write_verilog\n"); + log(" create a Verilog test bench to test simlib and write_verilog\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design*) |