diff options
Diffstat (limited to 'passes/tests')
| -rw-r--r-- | passes/tests/test_autotb.cc | 13 | ||||
| -rw-r--r-- | passes/tests/test_cell.cc | 4 |
2 files changed, 13 insertions, 4 deletions
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 42e8a61ea..19f21493d 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -81,6 +81,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("integer i;\n"); f << stringf("integer file;\n\n"); + f << stringf("reg [1023:0] filename;\n\n"); f << stringf("reg [31:0] xorshift128_x = 123456789;\n"); f << stringf("reg [31:0] xorshift128_y = 362436069;\n"); @@ -305,9 +306,15 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s } f << stringf("initial begin\n"); - f << stringf("\t// $dumpfile(\"testbench.vcd\");\n"); - f << stringf("\t// $dumpvars(0, testbench);\n"); - f << stringf("\tfile = $fopen(`outfile);\n"); + f << stringf("\tif ($value$plusargs(\"VCD=%%s\", filename)) begin\n"); + f << stringf("\t\t$dumpfile(filename);\n"); + f << stringf("\t\t$dumpvars(0, testbench);\n"); + f << stringf("\tend\n"); + f << stringf("\tif ($value$plusargs(\"OUT=%%s\", filename)) begin\n"); + f << stringf("\t\tfile = $fopen(filename);\n"); + f << stringf("\tend else begin\n"); + f << stringf("\t\tfile = $fopen(`outfile);\n"); + f << stringf("\tend\n"); for (auto module : design->modules()) if (!module->get_bool_attribute(ID::gentb_skip)) f << stringf("\t%s;\n", idy(module->name.str(), "test").c_str()); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index cdbe922b2..c6801007d 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -264,7 +264,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->setPort(ID::Y, wire); } - if (muxdiv && cell_type.in(ID($div), ID($mod))) { + if (muxdiv && cell_type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B)); auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y))); module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y)); @@ -839,6 +839,8 @@ struct TestCellPass : public Pass { cell_types[ID($mul)] = "ABSY"; cell_types[ID($div)] = "ABSY"; cell_types[ID($mod)] = "ABSY"; + cell_types[ID($divfloor)] = "ABSY"; + cell_types[ID($modfloor)] = "ABSY"; // cell_types[ID($pow)] = "ABsY"; cell_types[ID($logic_not)] = "ASY"; |