diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/connect.cc | 2 | ||||
| -rw-r--r-- | passes/cmds/select.cc | 2 | ||||
| -rw-r--r-- | passes/proc/proc_init.cc | 2 | ||||
| -rw-r--r-- | passes/sat/sat.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/extract.cc | 2 | ||||
| -rw-r--r-- | passes/tests/test_autotb.cc | 2 | ||||
| -rw-r--r-- | passes/tests/test_cell.cc | 2 |
7 files changed, 7 insertions, 7 deletions
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index e0b1ce051..52611cf44 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -50,7 +50,7 @@ struct ConnectPass : public Pass { log(" connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>\n"); log("\n"); log("Create a connection. This is equivalent to adding the statement 'assign\n"); - log("<lhs-expr> = <rhs-expr>;' to the verilog input. Per default, all existing\n"); + log("<lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing\n"); log("drivers for <lhs-expr> are unconnected. This can be overwritten by using\n"); log("the -nounset option.\n"); log("\n"); diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index b4219db2c..f18e40228 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -1061,7 +1061,7 @@ struct SelectPass : public Pass { log(" like %%d but swap the roles of two top sets on the stack\n"); log("\n"); log(" %%c\n"); - log(" create a copy of the top set rom the stack and push it\n"); + log(" create a copy of the top set from the stack and push it\n"); log("\n"); log(" %%x[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n"); log(" expand top set <num1> num times according to the specified rules.\n"); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 1d6738058..633d4e58a 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -93,7 +93,7 @@ struct ProcInitPass : public Pass { log("\n"); log(" proc_init [selection]\n"); log("\n"); - log("This pass extracts the 'init' actions from processes (generated from verilog\n"); + log("This pass extracts the 'init' actions from processes (generated from Verilog\n"); log("'initial' blocks) and sets the initial value to the 'init' attribute on the\n"); log("respective wire.\n"); log("\n"); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index ed6526fba..c83286924 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -990,7 +990,7 @@ struct SatPass : public Pass { log("is passed, a temporal induction proof is performed.\n"); log("\n"); log(" -tempinduct\n"); - log(" Perform a temporal induction proof. In a temporalinduction proof it is\n"); + log(" Perform a temporal induction proof. In a temporal induction proof it is\n"); log(" proven that the condition holds forever after the number of time steps\n"); log(" specified using -seq.\n"); log("\n"); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 3c24524df..68a7fc1f6 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -361,7 +361,7 @@ struct ExtractPass : public Pass { log("\n"); log("This pass looks for subcircuits that are isomorphic to any of the modules\n"); log("in the given map file and replaces them with instances of this modules. The\n"); - log("map file can be a verilog source file (*.v) or an ilang file (*.il).\n"); + log("map file can be a Verilog source file (*.v) or an ilang file (*.il).\n"); log("\n"); log(" -map <map_file>\n"); log(" use the modules in this file as reference. This option can be used\n"); diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 659f0bb69..bb516fca9 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -310,7 +310,7 @@ struct TestAutotbBackend : public Backend { log("\n"); log(" test_autotb [options] [filename]\n"); log("\n"); - log("Automatically create primitive verilog test benches for all modules in the\n"); + log("Automatically create primitive Verilog test benches for all modules in the\n"); log("design. The generated testbenches toggle the input pins of the module in\n"); log("a semi-random manner and dumps the resulting output signals.\n"); log("\n"); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index bd3749b71..abac62231 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -556,7 +556,7 @@ struct TestCellPass : public Pass { log(" print additional debug information to the console\n"); log("\n"); log(" -vlog {filename}\n"); - log(" create a verilog test bench to test simlib and write_verilog\n"); + log(" create a Verilog test bench to test simlib and write_verilog\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design*) |