4 files changed, 39 insertions, 30 deletions
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index eeef24bde..e0d428811 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -668,6 +668,10 @@ struct ShowPass : public Pass {
 		log("    -notitle\n");
 		log("        do not add the module name as graph title to the dot file\n");
 		log("\n");
+		log("    -nobg\n");
+		log("        don't run viewer in the background, IE wait for the viewer tool to\n");
+		log("        exit before returning\n");
+		log("\n");
 		log("When no <format> is specified, 'dot' is used. When no <format> and <viewer> is\n");
 		log("specified, 'xdot' is used to display the schematic (POSIX systems only).\n");
 		log("\n");
@@ -706,6 +710,7 @@ struct ShowPass : public Pass {
 		bool flag_abbreviate = true;
 		bool flag_notitle = false;
 		bool custom_prefix = false;
+		std::string background = "&";
 		RTLIL::IdString colorattr;
 
 		size_t argidx;
@@ -787,6 +792,10 @@ struct ShowPass : public Pass {
 				flag_notitle = true;
 				continue;
 			}
+			if (arg == "-nobg") {
+				background= "";
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -859,21 +868,19 @@ struct ShowPass : public Pass {
 				// system()/cmd.exe does not understand single quotes nor
 				// background tasks on Windows. So we have to pause yosys
 				// until the viewer exits.
-				#define VIEW_CMD "%s \"%s\""
+				std::string cmd = stringf("%s \"%s\"", viewer_exe.c_str(), out_file.c_str());
 			#else
-				#define VIEW_CMD "%s '%s' &"
+				std::string cmd = stringf("%s '%s' %s", viewer_exe.c_str(), out_file.c_str(), background.c_str());
 			#endif
-			std::string cmd = stringf(VIEW_CMD, viewer_exe.c_str(), out_file.c_str());
-			#undef VIEW_CMD
 			log("Exec: %s\n", cmd.c_str());
 			if (run_command(cmd) != 0)
 				log_cmd_error("Shell command failed!\n");
 		} else
 		if (format.empty()) {
 			#ifdef __APPLE__
-			std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' &", getuid(), dot_file.c_str(), dot_file.c_str());
+			std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str());
 			#else
-			std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' &", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str());
+			std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str());
 			#endif
 			log("Exec: %s\n", cmd.c_str());
 			if (run_command(cmd) != 0)
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 2f69b3d4c..f5bb40050 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -51,20 +51,26 @@ struct keep_cache_t
 		if (cache.count(module))
 			return cache.at(module);
 
-		cache[module] = true;
-		if (!module->get_bool_attribute(ID::keep)) {
-			bool found_keep = false;
+		bool found_keep = false;
+		if (module->get_bool_attribute(ID::keep))
+			found_keep = true;
+		else
 			for (auto cell : module->cells())
-				if (query(cell)) found_keep = true;
-			cache[module] = found_keep;
-		}
+				if (query(cell, true /* ignore_specify */)) {
+					found_keep = true;
+					break;
+				}
+		cache[module] = found_keep;
 
-		return cache[module];
+		return found_keep;
 	}
 
-	bool query(Cell *cell)
+	bool query(Cell *cell, bool ignore_specify = false)
 	{
-		if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($specify2), ID($specify3), ID($specrule)))
+		if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
+			return true;
+
+		if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
 			return true;
 
 		if (cell->has_keep_attr())
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 7071f0de4..54605f90e 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -192,20 +192,9 @@ void prep_dff(RTLIL::Module *module)
 		clkdomain_t key(abc9_clock);
 
 		auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
-		auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
-		log_assert(r2.second);
-
-		Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
-		if (abc9_init_wire == NULL)
-			log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-		log_assert(GetSize(abc9_init_wire) == 1);
-		SigSpec abc9_init = assign_map(abc9_init_wire);
-		if (!abc9_init.is_fully_const())
-			log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-		if (abc9_init == State::S1)
-			log_error("'%s.init' in module '%s' has value 1'b1 which is not supported by 'abc9 -dff'.\n", cell->name.c_str(), log_id(module));
-		r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
+		auto r2  = cell->attributes.insert(ID(abc9_mergeability));;
 		log_assert(r2.second);
+		r2.first->second = r.first->second;
 	}
 
 	RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
@@ -763,13 +752,11 @@ void reintegrate(RTLIL::Module *module)
 				continue;
 			}
 
-#ifndef NDEBUG
 			RTLIL::Module* box_module = design->module(existing_cell->type);
 			IdString derived_type = box_module->derive(design, existing_cell->parameters);
 			RTLIL::Module* derived_module = design->module(derived_type);
 			log_assert(derived_module);
 			log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
-#endif
 			mapped_cell->type = existing_cell->type;
 
 			RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 531ac2b99..a6e4fac14 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -423,6 +423,15 @@ struct IopadmapPass : public Pass {
 					}
 				}
 
+				if (wire->port_output) {
+					auto jt = new_wire->attributes.find(ID(init));
+					// For output ports, move \init attributes from old wire to new wire
+					if (jt != new_wire->attributes.end()) {
+						wire->attributes[ID(init)] = std::move(jt->second);
+						new_wire->attributes.erase(jt);
+					}
+				}
+
 				wire->port_id = 0;
 				wire->port_input = false;
 				wire->port_output = false;