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-rw-r--r--passes/cmds/design.cc3
-rw-r--r--passes/cmds/exec.cc2
-rw-r--r--passes/hierarchy/hierarchy.cc132
-rw-r--r--passes/sat/eval.cc90
-rw-r--r--passes/sat/freduce.cc28
5 files changed, 124 insertions, 131 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index f807c0e58..7ea0be9ee 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -18,6 +18,7 @@
*/
#include "kernel/yosys.h"
+#include "frontends/verilog/preproc.h"
#include "frontends/ast/ast.h"
YOSYS_NAMESPACE_BEGIN
@@ -348,7 +349,7 @@ struct DesignPass : public Pass {
delete node;
design->verilog_globals.clear();
- design->verilog_defines.clear();
+ design->verilog_defines->clear();
}
if (!load_name.empty() || pop_mode)
diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc
index 399cb0ebb..7eeefe705 100644
--- a/passes/cmds/exec.cc
+++ b/passes/cmds/exec.cc
@@ -22,11 +22,13 @@
#include <cstdio>
#if defined(_WIN32)
+# include <csignal>
# define WIFEXITED(x) 1
# define WIFSIGNALED(x) 0
# define WIFSTOPPED(x) 0
# define WEXITSTATUS(x) ((x) & 0xff)
# define WTERMSIG(x) SIGTERM
+# define WSTOPSIG(x) 0
#else
# include <sys/wait.h>
#endif
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index fa4a8ea29..3f4fe502d 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -42,11 +42,10 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
{
std::set<RTLIL::IdString> found_celltypes;
- for (auto i1 : design->modules_)
- for (auto i2 : i1.second->cells_)
+ for (auto mod : design->modules())
+ for (auto cell : mod->cells())
{
- RTLIL::Cell *cell = i2.second;
- if (design->has(cell->type))
+ if (design->module(cell->type) != nullptr)
continue;
if (cell->type.begins_with("$__"))
continue;
@@ -62,15 +61,15 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
std::map<RTLIL::IdString, int> portwidths;
log("Generate module for cell type %s:\n", celltype.c_str());
- for (auto i1 : design->modules_)
- for (auto i2 : i1.second->cells_)
- if (i2.second->type == celltype) {
- for (auto &conn : i2.second->connections()) {
+ for (auto mod : design->modules())
+ for (auto cell : mod->cells())
+ if (cell->type == celltype) {
+ for (auto &conn : cell->connections()) {
if (conn.first[0] != '$')
portnames.insert(conn.first);
portwidths[conn.first] = max(portwidths[conn.first], conn.second.size());
}
- for (auto &para : i2.second->parameters)
+ for (auto &para : cell->parameters)
parameters.insert(para.first);
}
@@ -168,26 +167,24 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// If any of the ports are actually interface ports, we will always need to
// reprocess the module:
if(!module->get_bool_attribute("\\interfaces_replaced_in_module")) {
- for (auto &wire : module->wires_) {
- if ((wire.second->port_input || wire.second->port_output) && wire.second->get_bool_attribute("\\is_interface"))
+ for (auto wire : module->wires()) {
+ if ((wire->port_input || wire->port_output) && wire->get_bool_attribute("\\is_interface"))
has_interface_ports = true;
}
}
// Always keep track of all derived interfaces available in the current module in 'interfaces_in_module':
dict<RTLIL::IdString, RTLIL::Module*> interfaces_in_module;
- for (auto &cell_it : module->cells_)
+ for (auto cell : module->cells())
{
- RTLIL::Cell *cell = cell_it.second;
if(cell->get_bool_attribute("\\is_interface")) {
- RTLIL::Module *intf_module = design->modules_[cell->type];
+ RTLIL::Module *intf_module = design->module(cell->type);
interfaces_in_module[cell->name] = intf_module;
}
}
- for (auto &cell_it : module->cells_)
+ for (auto cell : module->cells())
{
- RTLIL::Cell *cell = cell_it.second;
bool has_interfaces_not_found = false;
std::vector<RTLIL::IdString> connections_to_remove;
@@ -208,11 +205,11 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
dict<RTLIL::IdString, RTLIL::Module*> interfaces_to_add_to_submodule;
dict<RTLIL::IdString, RTLIL::IdString> modports_used_in_submodule;
- if (design->modules_.count(cell->type) == 0)
+ if (design->module(cell->type) == nullptr)
{
- if (design->modules_.count("$abstract" + cell->type.str()))
+ if (design->module("$abstract" + cell->type.str()) != nullptr)
{
- cell->type = design->modules_.at("$abstract" + cell->type.str())->derive(design, cell->parameters);
+ cell->type = design->module("$abstract" + cell->type.str())->derive(design, cell->parameters);
cell->parameters.clear();
did_something = true;
continue;
@@ -246,7 +243,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
continue;
loaded_module:
- if (design->modules_.count(cell->type) == 0)
+ if (design->module(cell->type) == nullptr)
log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str());
did_something = true;
} else {
@@ -256,7 +253,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// Go over all connections and see if any of them are SV interfaces. If they are, then add the replacements to
// some lists, so that the ports for sub-modules can be replaced further down:
for (auto &conn : cell->connections()) {
- if(mod->wires_.count(conn.first) != 0 && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list
+ if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list
//const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_type");
//for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness)
//}
@@ -285,11 +282,11 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
if (nexactmatch != 0) // Choose the one with the plain name if it exists
interface_name2 = interface_name;
RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name2);
- for (auto &mod_wire : mod_replace_ports->wires_) { // Go over all wires in interface, and add replacements to lists.
- std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire.first);
- std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire.first);
+ for (auto mod_wire : mod_replace_ports->wires()) { // Go over all wires in interface, and add replacements to lists.
+ std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire->name);
+ std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire);
connections_to_add_name.push_back(RTLIL::IdString(signal_name1));
- if(module->wires_.count(signal_name2) == 0) {
+ if(module->wire(signal_name2) == nullptr) {
log_error("Could not find signal '%s' in '%s'\n", signal_name2.c_str(), log_id(module->name));
}
else {
@@ -344,9 +341,9 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
}
}
- RTLIL::Module *mod = design->modules_[cell->type];
+ RTLIL::Module *mod = design->module(cell->type);
- if (design->modules_.at(cell->type)->get_blackbox_attribute()) {
+ if (design->module(cell->type)->get_blackbox_attribute()) {
if (flag_simcheck)
log_error("Module `%s' referenced in module `%s' in cell `%s' is a blackbox/whitebox module.\n",
cell->type.c_str(), module->name.c_str(), cell->name.c_str());
@@ -389,7 +386,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// an interface instance:
if (mod->get_bool_attribute("\\is_interface") && cell->get_bool_attribute("\\module_not_derived")) {
cell->set_bool_attribute("\\is_interface");
- RTLIL::Module *derived_module = design->modules_[cell->type];
+ RTLIL::Module *derived_module = design->module(cell->type);
interfaces_in_module[cell->name] = derived_module;
did_something = true;
}
@@ -414,25 +411,25 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
RTLIL::Cell *cell = it.first;
int idx = it.second.first, num = it.second.second;
- if (design->modules_.count(cell->type) == 0)
+ if (design->module(cell->type) == nullptr)
log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
- RTLIL::Module *mod = design->modules_[cell->type];
+ RTLIL::Module *mod = design->module(cell->type);
for (auto &conn : cell->connections_) {
int conn_size = conn.second.size();
RTLIL::IdString portname = conn.first;
if (portname.begins_with("$")) {
int port_id = atoi(portname.substr(1).c_str());
- for (auto &wire_it : mod->wires_)
- if (wire_it.second->port_id == port_id) {
- portname = wire_it.first;
+ for (auto wire : mod->wires())
+ if (wire->port_id == port_id) {
+ portname = wire->name;
break;
}
}
- if (mod->wires_.count(portname) == 0)
+ if (mod->wire(portname) == nullptr)
log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
- int port_size = mod->wires_.at(portname)->width;
+ int port_size = mod->wire(portname)->width;
if (conn_size == port_size || conn_size == 0)
continue;
if (conn_size != port_size*num)
@@ -470,21 +467,21 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
hierarchy_worker(design, used, top, 0);
std::vector<RTLIL::Module*> del_modules;
- for (auto &it : design->modules_)
- if (used.count(it.second) == 0)
- del_modules.push_back(it.second);
+ for (auto mod : design->modules())
+ if (used.count(mod) == 0)
+ del_modules.push_back(mod);
else {
// Now all interface ports must have been exploded, and it is hence
// safe to delete all of the remaining dummy interface ports:
pool<RTLIL::Wire*> del_wires;
- for(auto &wire : it.second->wires_) {
- if ((wire.second->port_input || wire.second->port_output) && wire.second->get_bool_attribute("\\is_interface")) {
- del_wires.insert(wire.second);
+ for(auto wire : mod->wires()) {
+ if ((wire->port_input || wire->port_output) && wire->get_bool_attribute("\\is_interface")) {
+ del_wires.insert(wire);
}
}
if (del_wires.size() > 0) {
- it.second->remove(del_wires);
- it.second->fixup_ports();
+ mod->remove(del_wires);
+ mod->fixup_ports();
}
}
@@ -493,9 +490,8 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
if (!purge_lib && mod->get_blackbox_attribute())
continue;
log("Removing unused module `%s'.\n", mod->name.c_str());
- design->modules_.erase(mod->name);
+ design->remove(mod);
del_counter++;
- delete mod;
}
log("Removed %d unused modules.\n", del_counter);
@@ -817,9 +813,9 @@ struct HierarchyPass : public Pass {
log_push();
if (top_mod == nullptr)
- for (auto &mod_it : design->modules_)
- if (mod_it.second->get_bool_attribute("\\top"))
- top_mod = mod_it.second;
+ for (auto mod : design->modules())
+ if (mod->get_bool_attribute("\\top"))
+ top_mod = mod;
if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
IdString top_name = top_mod->name.substr(strlen("$abstract"));
@@ -862,11 +858,11 @@ struct HierarchyPass : public Pass {
log_error("Design has no top module.\n");
if (top_mod != NULL) {
- for (auto &mod_it : design->modules_)
- if (mod_it.second == top_mod)
- mod_it.second->attributes["\\initial_top"] = RTLIL::Const(1);
+ for (auto mod : design->modules())
+ if (mod == top_mod)
+ mod->attributes["\\initial_top"] = RTLIL::Const(1);
else
- mod_it.second->attributes.erase("\\initial_top");
+ mod->attributes.erase("\\initial_top");
}
bool did_something = true;
@@ -900,9 +896,9 @@ struct HierarchyPass : public Pass {
// Delete modules marked as 'to_delete':
std::vector<RTLIL::Module *> modules_to_delete;
- for(auto &mod_it : design->modules_) {
- if (mod_it.second->get_bool_attribute("\\to_delete")) {
- modules_to_delete.push_back(mod_it.second);
+ for(auto mod : design->modules()) {
+ if (mod->get_bool_attribute("\\to_delete")) {
+ modules_to_delete.push_back(mod);
}
}
for(size_t i=0; i<modules_to_delete.size(); i++) {
@@ -917,12 +913,12 @@ struct HierarchyPass : public Pass {
}
if (top_mod != NULL) {
- for (auto &mod_it : design->modules_) {
- if (mod_it.second == top_mod)
- mod_it.second->attributes["\\top"] = RTLIL::Const(1);
+ for (auto mod : design->modules()) {
+ if (mod == top_mod)
+ mod->attributes["\\top"] = RTLIL::Const(1);
else
- mod_it.second->attributes.erase("\\top");
- mod_it.second->attributes.erase("\\initial_top");
+ mod->attributes.erase("\\top");
+ mod->attributes.erase("\\initial_top");
}
}
@@ -941,22 +937,20 @@ struct HierarchyPass : public Pass {
std::map<std::pair<RTLIL::Module*,int>, RTLIL::IdString> pos_map;
std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work;
- for (auto &mod_it : design->modules_)
- for (auto &cell_it : mod_it.second->cells_) {
- RTLIL::Cell *cell = cell_it.second;
- if (design->modules_.count(cell->type) == 0)
+ for (auto mod : design->modules())
+ for (auto cell : mod->cells()) {
+ if (design->module(cell->type) == nullptr)
continue;
for (auto &conn : cell->connections())
if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
- pos_mods.insert(design->modules_.at(cell->type));
- pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell));
+ pos_mods.insert(design->module(cell->type));
+ pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod, cell));
break;
}
}
for (auto module : pos_mods)
- for (auto &wire_it : module->wires_) {
- RTLIL::Wire *wire = wire_it.second;
+ for (auto wire : module->wires()) {
if (wire->port_id > 0)
pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = wire->name;
}
@@ -970,7 +964,7 @@ struct HierarchyPass : public Pass {
for (auto &conn : cell->connections())
if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
int id = atoi(conn.first.c_str()+1);
- std::pair<RTLIL::Module*,int> key(design->modules_.at(cell->type), id);
+ std::pair<RTLIL::Module*,int> key(design->module(cell->type), id);
if (pos_map.count(key) == 0) {
log(" Failed to map positional argument %d of cell %s.%s (%s).\n",
id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index e0bb439f4..148480d55 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -88,25 +88,24 @@ struct BruteForceEquivChecker
mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
{
log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
- for (auto &w : mod1->wires_)
+ for (auto w : mod1->wires())
{
- RTLIL::Wire *wire1 = w.second;
- if (wire1->port_id == 0)
+ if (w->port_id == 0)
continue;
- if (mod2->wires_.count(wire1->name) == 0)
- log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", wire1->name.c_str());
+ if (mod2->wire(w->name) == nullptr)
+ log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", w->name.c_str());
- RTLIL::Wire *wire2 = mod2->wires_.at(wire1->name);
- if (wire1->width != wire2->width || wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output)
- log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", wire1->name.c_str());
+ RTLIL::Wire *w2 = mod2->wire(w->name);
+ if (w->width != w2->width || w->port_input != w2->port_input || w->port_output != w2->port_output)
+ log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", w->name.c_str());
- if (wire1->port_input) {
- mod1_inputs.append(wire1);
- mod2_inputs.append(wire2);
+ if (w->port_input) {
+ mod1_inputs.append(w);
+ mod2_inputs.append(w2);
} else {
- mod1_outputs.append(wire1);
- mod2_outputs.append(wire2);
+ mod1_outputs.append(w);
+ mod2_outputs.append(w2);
}
}
@@ -148,17 +147,17 @@ struct VlogHammerReporter
SatGen satgen(ez.get(), &sigmap);
satgen.model_undef = model_undef;
- for (auto &c : module->cells_)
- if (!satgen.importCell(c.second))
- log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
+ for (auto c : module->cells())
+ if (!satgen.importCell(c))
+ log_error("Failed to import cell %s (type %s) to SAT database.\n", log_id(c->name), log_id(c->type));
ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
- std::vector<int> y_vec = satgen.importDefSigSpec(module->wires_.at("\\y"));
+ std::vector<int> y_vec = satgen.importDefSigSpec(module->wire("\\y"));
std::vector<bool> y_values;
if (model_undef) {
- std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wires_.at("\\y"));
+ std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire("\\y"));
y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end());
}
@@ -253,7 +252,7 @@ struct VlogHammerReporter
std::vector<RTLIL::State> bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width);
for (int i = 0; i < int(inputs.size()); i++) {
- RTLIL::Wire *wire = module->wires_.at(inputs[i]);
+ RTLIL::Wire *wire = module->wire(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
@@ -263,21 +262,21 @@ struct VlogHammerReporter
if (module == modules.front()) {
RTLIL::SigSpec sig(wire);
if (!ce.eval(sig))
- log_error("Can't read back value for port %s!\n", RTLIL::id2cstr(inputs[i]));
+ log_error("Can't read back value for port %s!\n", log_id(inputs[i]));
input_pattern_list += stringf(" %s", sig.as_const().as_string().c_str());
- log("++PAT++ %d %s %s #\n", idx, RTLIL::id2cstr(inputs[i]), sig.as_const().as_string().c_str());
+ log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string().c_str());
}
}
- if (module->wires_.count("\\y") == 0)
- log_error("No output wire (y) found in module %s!\n", RTLIL::id2cstr(module->name));
+ if (module->wire("\\y") == nullptr)
+ log_error("No output wire (y) found in module %s!\n", log_id(module->name));
- RTLIL::SigSpec sig(module->wires_.at("\\y"));
+ RTLIL::SigSpec sig(module->wire("\\y"));
RTLIL::SigSpec undef;
while (!ce.eval(sig, undef)) {
- // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef));
- log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
+ // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", log_id(module->name), log_signal(sig), log_signal(undef));
+ log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), log_id(module->name));
ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
}
@@ -289,7 +288,7 @@ struct VlogHammerReporter
sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
} else if (rtl_sig.size() > 0) {
if (rtl_sig.size() != sig.size())
- log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
+ log_error("Output (y) has a different width in module %s compared to rtl!\n", log_id(module->name));
for (int i = 0; i < GetSize(sig); i++)
if (rtl_sig[i] == RTLIL::State::Sx)
sig[i] = RTLIL::State::Sx;
@@ -307,10 +306,10 @@ struct VlogHammerReporter
{
for (auto name : split(module_list, ",")) {
RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name);
- if (design->modules_.count(esc_name) == 0)
+ if (design->module(esc_name) == nullptr)
log_error("Can't find module %s in current design!\n", name.c_str());
log("Using module %s (%s).\n", esc_name.c_str(), name.c_str());
- modules.push_back(design->modules_.at(esc_name));
+ modules.push_back(design->module(esc_name));
module_names.push_back(name);
}
@@ -319,11 +318,11 @@ struct VlogHammerReporter
int width = -1;
RTLIL::IdString esc_name = RTLIL::escape_id(name);
for (auto mod : modules) {
- if (mod->wires_.count(esc_name) == 0)
- log_error("Can't find input %s in module %s!\n", name.c_str(), RTLIL::id2cstr(mod->name));
- RTLIL::Wire *port = mod->wires_.at(esc_name);
+ if (mod->wire(esc_name) == nullptr)
+ log_error("Can't find input %s in module %s!\n", name.c_str(), log_id(mod->name));
+ RTLIL::Wire *port = mod->wire(esc_name);
if (!port->port_input || port->port_output)
- log_error("Wire %s in module %s is not an input!\n", name.c_str(), RTLIL::id2cstr(mod->name));
+ log_error("Wire %s in module %s is not an input!\n", name.c_str(), log_id(mod->name));
if (width >= 0 && width != port->width)
log_error("Port %s has different sizes in the different modules!\n", name.c_str());
width = port->width;
@@ -415,11 +414,11 @@ struct EvalPass : public Pass {
/* this should only be used for regression testing of ConstEval -- see vloghammer */
std::string mod1_name = RTLIL::escape_id(args[++argidx]);
std::string mod2_name = RTLIL::escape_id(args[++argidx]);
- if (design->modules_.count(mod1_name) == 0)
+ if (design->module(mod1_name) == nullptr)
log_error("Can't find module `%s'!\n", mod1_name.c_str());
- if (design->modules_.count(mod2_name) == 0)
+ if (design->module(mod2_name) == nullptr)
log_error("Can't find module `%s'!\n", mod2_name.c_str());
- BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
+ BruteForceEquivChecker checker(design->module(mod1_name), design->module(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
if (checker.errors > 0)
log_cmd_error("Modules are not equivalent!\n");
log("Verified %s = %s (using brute-force check on %d cases).\n",
@@ -441,13 +440,12 @@ struct EvalPass : public Pass {
extra_args(args, argidx, design);
RTLIL::Module *module = NULL;
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second)) {
- if (module)
- log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
- RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first));
- module = mod_it.second;
- }
+ for (auto mod : design->selected_modules()) {
+ if (module)
+ log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
+ log_id(module->name), log_id(mod->name));
+ module = mod;
+ }
if (module == NULL)
log_cmd_error("Can't perform EVAL on an empty selection!\n");
@@ -468,9 +466,9 @@ struct EvalPass : public Pass {
}
if (shows.size() == 0) {
- for (auto &it : module->wires_)
- if (it.second->port_output)
- shows.push_back(it.second->name.str());
+ for (auto w : module->wires())
+ if (w->port_output)
+ shows.push_back(w->name.str());
}
if (tables.empty())
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index f29631639..54016e528 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -614,29 +614,29 @@ struct FreduceWorker
int bits_full_total = 0;
std::vector<std::set<RTLIL::SigBit>> batches;
- for (auto &it : module->wires_)
- if (it.second->port_input) {
- batches.push_back(sigmap(it.second).to_sigbit_set());
- bits_full_total += it.second->width;
+ for (auto w : module->wires())
+ if (w->port_input) {
+ batches.push_back(sigmap(w).to_sigbit_set());
+ bits_full_total += w->width;
}
- for (auto &it : module->cells_) {
- if (ct.cell_known(it.second->type)) {
+ for (auto cell : module->cells()) {
+ if (ct.cell_known(cell->type)) {
std::set<RTLIL::SigBit> inputs, outputs;
- for (auto &port : it.second->connections()) {
+ for (auto &port : cell->connections()) {
std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
- if (ct.cell_output(it.second->type, port.first))
+ if (ct.cell_output(cell->type, port.first))
outputs.insert(bits.begin(), bits.end());
else
inputs.insert(bits.begin(), bits.end());
}
- std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(it.second, inputs);
+ std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(cell, inputs);
for (auto &bit : outputs)
drivers[bit] = drv;
batches.push_back(outputs);
bits_full_total += outputs.size();
}
- if (inv_mode && it.second->type == "$_NOT_")
- inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y"))));
+ if (inv_mode && cell->type == "$_NOT_")
+ inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\Y"))));
}
int bits_count = 0;
@@ -828,10 +828,8 @@ struct FreducePass : public Pass {
extra_args(args, argidx, design);
int bitcount = 0;
- for (auto &mod_it : design->modules_) {
- RTLIL::Module *module = mod_it.second;
- if (design->selected(module))
- bitcount += FreduceWorker(design, module).run();
+ for (auto module : design->selected_modules()) {
+ bitcount += FreduceWorker(design, module).run();
}
log("Rewired a total of %d signal bits.\n", bitcount);
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 19:00:02 +0000