diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/attrmap.cc | 19 |
2 files changed, 20 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f107f9947..5f448e37a 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -29,7 +29,7 @@ "&st; &if -g -K 6; &dch -f; &if {W}; &save; &load; "\ "&st; &if -g -K 6; &synch2; &if {W}; &save; &load" #else -#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps -l; &if {W} {D} -v; "/*"&mfs; "*/"&ps -l" +#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps -l; &if {W} {D} -v; &mfs; &ps -l" #endif diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index aa48e1125..a38638e0b 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -263,6 +263,25 @@ struct AttrmapPass : public Pass { for (auto cell : module->selected_cells()) attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->attributes); + + for (auto proc : module->processes) + { + if (!design->selected(module, proc.second)) + continue; + attrmap_apply(stringf("%s.%s", log_id(module), log_id(proc.first)), actions, proc.second->attributes); + + std::vector<RTLIL::CaseRule*> all_cases = {&proc.second->root_case}; + while (!all_cases.empty()) { + RTLIL::CaseRule *cs = all_cases.back(); + all_cases.pop_back(); + attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc.first)), actions, cs->attributes); + + for (auto &sw : cs->switches) { + attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc.first)), actions, sw->attributes); + all_cases.insert(all_cases.end(), sw->cases.begin(), sw->cases.end()); + } + } + } } } } |