diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/Makefile.inc | 2 | ||||
| -rw-r--r-- | passes/cmds/add.cc | 99 | ||||
| -rw-r--r-- | passes/cmds/exec.cc | 203 | ||||
| -rw-r--r-- | passes/cmds/logger.cc | 183 | ||||
| -rw-r--r-- | passes/cmds/select.cc | 376 | ||||
| -rw-r--r-- | passes/cmds/show.cc | 19 | ||||
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 6 | ||||
| -rw-r--r-- | passes/hierarchy/submod.cc | 136 | ||||
| -rw-r--r-- | passes/opt/opt_clean.cc | 18 | ||||
| -rw-r--r-- | passes/sat/miter.cc | 116 | ||||
| -rw-r--r-- | passes/techmap/abc.cc | 5 | ||||
| -rw-r--r-- | passes/techmap/abc9.cc | 57 | ||||
| -rw-r--r-- | passes/techmap/abc9_exe.cc | 4 | ||||
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 550 | ||||
| -rw-r--r-- | passes/techmap/deminout.cc | 3 | ||||
| -rw-r--r-- | passes/techmap/extract_counter.cc | 451 | ||||
| -rw-r--r-- | passes/techmap/iopadmap.cc | 101 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 2 |
18 files changed, 1683 insertions, 648 deletions
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 07a5d3ddc..60f20fa6d 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -1,4 +1,5 @@ +OBJS += passes/cmds/exec.o OBJS += passes/cmds/add.o OBJS += passes/cmds/delete.o OBJS += passes/cmds/design.o @@ -33,3 +34,4 @@ OBJS += passes/cmds/blackbox.o OBJS += passes/cmds/ltp.o OBJS += passes/cmds/bugpoint.o OBJS += passes/cmds/scratchpad.o +OBJS += passes/cmds/logger.o diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index dd05ac81f..c49b8bf5d 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -22,26 +22,61 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +static bool is_formal_celltype(const std::string &celltype) +{ + if(celltype == "assert" || celltype == "assume" || celltype == "live" || celltype == "fair" || celltype == "cover") + return true; + else + return false; +} + +static void add_formal(RTLIL::Module *module, const std::string &celltype, const std::string &name, const std::string &enable_name) +{ + std::string escaped_name = RTLIL::escape_id(name); + std::string escaped_enable_name = (enable_name != "") ? RTLIL::escape_id(enable_name) : ""; + RTLIL::Wire *wire = module->wire(escaped_name); + log_assert(is_formal_celltype(celltype)); + + if (wire == nullptr) { + log_error("Could not find wire with name \"%s\".\n", name.c_str()); + } + else { + RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype); + formal_cell->setPort(ID(A), wire); + if(enable_name == "") { + formal_cell->setPort(ID(EN), State::S1); + log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str()); + } + else { + RTLIL::Wire *enable_wire = module->wire(escaped_enable_name); + if(enable_wire == nullptr) + log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str()); + + formal_cell->setPort(ID(EN), enable_wire); + log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str()); + } + } +} + static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global) { - RTLIL::Wire *wire = NULL; + RTLIL::Wire *wire = nullptr; name = RTLIL::escape_id(name); if (module->count_id(name) != 0) { - if (module->wires_.count(name) > 0) - wire = module->wires_.at(name); + wire = module->wire(name); - if (wire != NULL && wire->width != width) - wire = NULL; + if (wire != nullptr && wire->width != width) + wire = nullptr; - if (wire != NULL && wire->port_input != flag_input) - wire = NULL; + if (wire != nullptr && wire->port_input != flag_input) + wire = nullptr; - if (wire != NULL && wire->port_output != flag_output) - wire = NULL; + if (wire != nullptr && wire->port_output != flag_output) + wire = nullptr; - if (wire == NULL) + if (wire == nullptr) log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str()); log("Module %s already has such an object.\n", module->name.c_str()); @@ -53,7 +88,6 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n wire->port_output = flag_output; if (flag_input || flag_output) { - wire->port_id = module->wires_.size(); module->fixup_ports(); } @@ -63,21 +97,20 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n if (!flag_global) return; - for (auto &it : module->cells_) + for (auto cell : module->cells()) { - if (design->modules_.count(it.second->type) == 0) + RTLIL::Module *mod = design->module(cell->type); + if (mod == nullptr) continue; - - RTLIL::Module *mod = design->modules_.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; if (mod->get_blackbox_attribute()) continue; - if (it.second->hasPort(name)) + if (cell->hasPort(name)) continue; - it.second->setPort(name, wire); - log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); + cell->setPort(name, wire); + log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), cell->name.c_str(), cell->type.c_str()); } } @@ -106,6 +139,12 @@ struct AddPass : public Pass { log("selected modules.\n"); log("\n"); log("\n"); + log(" add {-assert|-assume|-live|-fair|-cover} <name1> [-if <name2>]\n"); + log("\n"); + log("Add an $assert, $assume, etc. cell connected to a wire named name1, with its\n"); + log("enable signal optionally connected to a wire named name2 (default: 1'b1).\n"); + log("\n"); + log("\n"); log(" add -mod <name[s]>\n"); log("\n"); log("Add module[s] with the specified name[s].\n"); @@ -115,6 +154,7 @@ struct AddPass : public Pass { { std::string command; std::string arg_name; + std::string enable_name = ""; bool arg_flag_input = false; bool arg_flag_output = false; bool arg_flag_global = false; @@ -144,6 +184,17 @@ struct AddPass : public Pass { argidx++; break; } + if (arg.length() > 0 && arg[0] == '-' && is_formal_celltype(arg.substr(1))) { + if (argidx + 1 >= args.size()) + break; + command = arg.substr(1); + arg_name = args[++argidx]; + if (argidx + 2 < args.size() && args[argidx + 1] == "-if") { + enable_name = args[argidx + 2]; + argidx += 2; + } + continue; + } break; } @@ -155,17 +206,23 @@ struct AddPass : public Pass { extra_args(args, argidx, design); - for (auto &mod : design->modules_) + bool selected_anything = false; + for (auto module : design->modules()) { - RTLIL::Module *module = mod.second; + log_assert(module != nullptr); if (!design->selected_whole_module(module->name)) continue; if (module->get_bool_attribute("\\blackbox")) continue; - if (command == "wire") + selected_anything = true; + if (is_formal_celltype(command)) + add_formal(module, command, arg_name, enable_name); + else if (command == "wire") add_wire(design, module, arg_name, arg_width, arg_flag_input, arg_flag_output, arg_flag_global); } + if (!selected_anything) + log_warning("No modules selected, or only blackboxes. Nothing was added.\n"); } } AddPass; diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc new file mode 100644 index 000000000..399cb0ebb --- /dev/null +++ b/passes/cmds/exec.cc @@ -0,0 +1,203 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/log.h" +#include <cstdio> + +#if defined(_WIN32) +# define WIFEXITED(x) 1 +# define WIFSIGNALED(x) 0 +# define WIFSTOPPED(x) 0 +# define WEXITSTATUS(x) ((x) & 0xff) +# define WTERMSIG(x) SIGTERM +#else +# include <sys/wait.h> +#endif + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct ExecPass : public Pass { + ExecPass() : Pass("exec", "execute commands in the operating system shell") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" exec [options] -- [command]\n"); + log("\n"); + log("Execute a command in the operating system shell. All supplied arguments are\n"); + log("concatenated and passed as a command to popen(3). Whitespace is not guaranteed\n"); + log("to be preserved, even if quoted. stdin and stderr are not connected, while stdout is\n"); + log("logged unless the \"-q\" option is specified.\n"); + log("\n"); + log("\n"); + log(" -q\n"); + log(" Suppress stdout and stderr from subprocess\n"); + log("\n"); + log(" -expect-return <int>\n"); + log(" Generate an error if popen() does not return specified value.\n"); + log(" May only be specified once; the final specified value is controlling\n"); + log(" if specified multiple times.\n"); + log("\n"); + log(" -expect-stdout <regex>\n"); + log(" Generate an error if the specified regex does not match any line\n"); + log(" in subprocess's stdout. May be specified multiple times.\n"); + log("\n"); + log(" -not-expect-stdout <regex>\n"); + log(" Generate an error if the specified regex matches any line\n"); + log(" in subprocess's stdout. May be specified multiple times.\n"); + log("\n"); + log("\n"); + log(" Example: exec -q -expect-return 0 -- echo \"bananapie\" | grep \"nana\"\n"); + log("\n"); + log("\n"); + } + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + { + std::string cmd = ""; + char buf[1024] = {}; + std::string linebuf = ""; + bool flag_cmd = false; + bool flag_quiet = false; + bool flag_expect_return = false; + int expect_return_value = 0; + bool flag_expect_stdout = false; + struct expect_stdout_elem { + bool matched; + bool polarity; //true: this regex must match at least one line + //false: this regex must not match any line + std::string str; + YS_REGEX_TYPE re; + + expect_stdout_elem() : matched(false), polarity(true), str(), re(){}; + }; + std::vector<expect_stdout_elem> expect_stdout; + + if(args.size() == 0) + log_cmd_error("No command provided.\n"); + + for(size_t argidx = 1; argidx < args.size(); ++argidx) { + if (flag_cmd) { + cmd += args[argidx] + (argidx != (args.size() - 1)? " " : ""); + } else { + if (args[argidx] == "--") + flag_cmd = true; + else if (args[argidx] == "-q") + flag_quiet = true; + else if (args[argidx] == "-expect-return") { + flag_expect_return = true; + ++argidx; + if (argidx >= args.size()) + log_cmd_error("No expected return value specified.\n"); + + expect_return_value = atoi(args[argidx].c_str()); + } else if (args[argidx] == "-expect-stdout") { + flag_expect_stdout = true; + ++argidx; + if (argidx >= args.size()) + log_cmd_error("No expected regular expression specified.\n"); + + try{ + expect_stdout_elem x; + x.str = args[argidx]; + x.re = YS_REGEX_COMPILE(args[argidx]); + expect_stdout.push_back(x); + } catch (const YS_REGEX_NS::regex_error& e) { + log_cmd_error("Error in regex expression '%s' !\n", args[argidx].c_str()); + } + } else if (args[argidx] == "-not-expect-stdout") { + flag_expect_stdout = true; + ++argidx; + if (argidx >= args.size()) + log_cmd_error("No expected regular expression specified.\n"); + + try{ + expect_stdout_elem x; + x.str = args[argidx]; + x.re = YS_REGEX_COMPILE(args[argidx]); + x.polarity = false; + expect_stdout.push_back(x); + } catch (const YS_REGEX_NS::regex_error& e) { + log_cmd_error("Error in regex expression '%s' !\n", args[argidx].c_str()); + } + + } else + log_cmd_error("Unknown option \"%s\" or \"--\" doesn\'t precede command.", args[argidx].c_str()); + } + } + + log_header(design, "Executing command \"%s\".\n", cmd.c_str()); + log_push(); + + fflush(stdout); + bool keep_reading = true; + int status = 0; + int retval = 0; + +#ifndef EMSCRIPTEN + FILE *f = popen(cmd.c_str(), "r"); + if (f == nullptr) + log_cmd_error("errno %d after popen() returned NULL.\n", errno); + while (keep_reading) { + keep_reading = (fgets(buf, sizeof(buf), f) != nullptr); + linebuf += buf; + memset(buf, 0, sizeof(buf)); + + auto pos = linebuf.find('\n'); + while (pos != std::string::npos) { + std::string line = linebuf.substr(0, pos); + linebuf.erase(0, pos + 1); + if (!flag_quiet) + log("%s\n", line.c_str()); + + if (flag_expect_stdout) + for(auto &x : expect_stdout) + if (YS_REGEX_NS::regex_search(line, x.re)) + x.matched = true; + + pos = linebuf.find('\n'); + } + } + status = pclose(f); +#endif + + if(WIFEXITED(status)) { + retval = WEXITSTATUS(status); + } + else if(WIFSIGNALED(status)) { + retval = WTERMSIG(status); + } + else if(WIFSTOPPED(status)) { + retval = WSTOPSIG(status); + } + + if (flag_expect_return && retval != expect_return_value) + log_cmd_error("Return value %d did not match expected return value %d.\n", retval, expect_return_value); + + if (flag_expect_stdout) + for (auto &x : expect_stdout) + if (x.polarity ^ x.matched) + log_cmd_error("Command stdout did%s have a line matching given regex \"%s\".\n", (x.polarity? " not" : ""), x.str.c_str()); + + log_pop(); + } +} ExecPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/cmds/logger.cc b/passes/cmds/logger.cc new file mode 100644 index 000000000..9a27952d4 --- /dev/null +++ b/passes/cmds/logger.cc @@ -0,0 +1,183 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2020 Miodrag Milanovic <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct LoggerPass : public Pass { + LoggerPass() : Pass("logger", "set logger properties") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" logger [options]\n"); + log("\n"); + log("This command sets global logger properties, also available using command line\n"); + log("options.\n"); + log("\n"); + log(" -[no]time\n"); + log(" enable/disable display of timestamp in log output.\n"); + log("\n"); + log(" -[no]stderr\n"); + log(" enable/disable logging errors to stderr.\n"); + log("\n"); + log(" -warn regex\n"); + log(" print a warning for all log messages matching the regex.\n"); + log("\n"); + log(" -nowarn regex\n"); + log(" if a warning message matches the regex, it is printed as regular\n"); + log(" message instead.\n"); + log("\n"); + log(" -werror regex\n"); + log(" if a warning message matches the regex, it is printed as error\n"); + log(" message instead and the tool terminates with a nonzero return code.\n"); + log("\n"); + log(" -[no]debug\n"); + log(" globally enable/disable debug log messages.\n"); + log("\n"); + log(" -experimental <feature>\n"); + log(" do not print warnings for the specified experimental feature\n"); + log("\n"); + log(" -expect <type> <regex> <expected_count>\n"); + log(" expect log,warning or error to appear. In case of error return code is 0.\n"); + log("\n"); + log(" -expect-no-warnings\n"); + log(" gives error in case there is at least one warning that is not expected.\n"); + log("\n"); + } + + void execute(std::vector<std::string> args, RTLIL::Design * design) YS_OVERRIDE + { + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + + if (args[argidx] == "-time") { + log_time = true; + log("Enabled timestamp in logs.\n"); + continue; + } + if (args[argidx] == "-notime") { + log_time = false; + log("Disabled timestamp in logs.\n"); + continue; + } + if (args[argidx] == "-stderr") { + log_error_stderr = true; + log("Enabled loggint errors to stderr.\n"); + continue; + } + if (args[argidx] == "-nostderr") { + log_error_stderr = false; + log("Disabled loggint errors to stderr.\n"); + continue; + } + if (args[argidx] == "-warn" && argidx+1 < args.size()) { + std::string pattern = args[++argidx]; + if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); + try { + log("Added regex '%s' for warnings to warn list.\n", pattern.c_str()); + log_warn_regexes.push_back(YS_REGEX_COMPILE(pattern)); + } + catch (const YS_REGEX_NS::regex_error& e) { + log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str()); + } + continue; + } + if (args[argidx] == "-nowarn" && argidx+1 < args.size()) { + std::string pattern = args[++argidx]; + if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); + try { + log("Added regex '%s' for warnings to nowarn list.\n", pattern.c_str()); + log_nowarn_regexes.push_back(YS_REGEX_COMPILE(pattern)); + } + catch (const YS_REGEX_NS::regex_error& e) { + log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str()); + } + continue; + } + if (args[argidx] == "-werror" && argidx+1 < args.size()) { + std::string pattern = args[++argidx]; + if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); + try { + log("Added regex '%s' for warnings to werror list.\n", pattern.c_str()); + log_werror_regexes.push_back(YS_REGEX_COMPILE(pattern)); + } + catch (const YS_REGEX_NS::regex_error& e) { + log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str()); + } + continue; + } + if (args[argidx] == "-debug") { + log_force_debug = 1; + log("Enabled debug log messages.\n"); + continue; + } + if (args[argidx] == "-nodebug") { + log_force_debug = 0; + log("Disabled debug log messages.\n"); + continue; + } + if (args[argidx] == "-experimental" && argidx+1 < args.size()) { + std::string value = args[++argidx]; + log("Added '%s' experimental ignore list.\n", value.c_str()); + log_experimentals_ignored.insert(value); + continue; + } + if (args[argidx] == "-expect" && argidx+3 < args.size()) { + std::string type = args[++argidx]; + if (type!="error" && type!="warning" && type!="log") + log_cmd_error("Expect command require type to be 'log', 'warning' or 'error' !\n"); + if (type=="error" && log_expect_error.size()>0) + log_cmd_error("Only single error message can be expected !\n"); + std::string pattern = args[++argidx]; + if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); + int count = atoi(args[++argidx].c_str()); + if (count<=0) + log_cmd_error("Number of expected messages must be higher then 0 !\n"); + if (type=="error" && count!=1) + log_cmd_error("Expected error message occurrences must be 1 !\n"); + log("Added regex '%s' for warnings to expected %s list.\n", pattern.c_str(), type.c_str()); + try { + if (type=="error") + log_expect_error.push_back(std::make_pair(YS_REGEX_COMPILE(pattern), LogExpectedItem(pattern, count))); + else if (type=="warning") + log_expect_warning.push_back(std::make_pair(YS_REGEX_COMPILE(pattern), LogExpectedItem(pattern, count))); + else + log_expect_log.push_back(std::make_pair(YS_REGEX_COMPILE(pattern), LogExpectedItem(pattern, count))); + } + catch (const YS_REGEX_NS::regex_error& e) { + log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str()); + } + continue; + } + if (args[argidx] == "-expect-no-warnings") { + log_expect_no_warnings = true; + continue; + } + break; + } + extra_args(args, argidx, design, false); + } +} LoggerPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 0f1f05ccb..b64b077e4 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -58,7 +58,7 @@ static bool match_attr_val(const RTLIL::Const &value, std::string pattern, char { RTLIL::SigSpec sig_value; - if (!RTLIL::SigSpec::parse(sig_value, NULL, pattern)) + if (!RTLIL::SigSpec::parse(sig_value, nullptr, pattern)) return false; RTLIL::Const pattern_value = sig_value.as_const(); @@ -152,27 +152,26 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs) RTLIL::Selection new_sel(false); - for (auto &mod_it : design->modules_) + for (auto mod : design->modules()) { - if (lhs.selected_whole_module(mod_it.first)) + if (lhs.selected_whole_module(mod->name)) continue; - if (!lhs.selected_module(mod_it.first)) { - new_sel.selected_modules.insert(mod_it.first); + if (!lhs.selected_module(mod->name)) { + new_sel.selected_modules.insert(mod->name); continue; } - RTLIL::Module *mod = mod_it.second; - for (auto &it : mod->wires_) - if (!lhs.selected_member(mod_it.first, it.first)) - new_sel.selected_members[mod->name].insert(it.first); + for (auto wire : mod->wires()) + if (!lhs.selected_member(mod->name, wire->name)) + new_sel.selected_members[mod->name].insert(wire->name); for (auto &it : mod->memories) - if (!lhs.selected_member(mod_it.first, it.first)) - new_sel.selected_members[mod->name].insert(it.first); - for (auto &it : mod->cells_) - if (!lhs.selected_member(mod_it.first, it.first)) + if (!lhs.selected_member(mod->name, it.first)) new_sel.selected_members[mod->name].insert(it.first); + for (auto cell : mod->cells()) + if (!lhs.selected_member(mod->name, cell->name)) + new_sel.selected_members[mod->name].insert(cell->name); for (auto &it : mod->processes) - if (!lhs.selected_member(mod_it.first, it.first)) + if (!lhs.selected_member(mod->name, it.first)) new_sel.selected_members[mod->name].insert(it.first); } @@ -223,15 +222,15 @@ static void select_op_random(RTLIL::Design *design, RTLIL::Selection &lhs, int c static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs) { - for (auto &mod_it : design->modules_) + for (auto mod : design->modules()) { - if (lhs.selected_whole_module(mod_it.first)) + if (lhs.selected_whole_module(mod->name)) { - for (auto &cell_it : mod_it.second->cells_) + for (auto cell : mod->cells()) { - if (design->modules_.count(cell_it.second->type) == 0) + if (design->module(cell->type) == nullptr) continue; - lhs.selected_modules.insert(cell_it.second->type); + lhs.selected_modules.insert(cell->type); } } } @@ -240,21 +239,21 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs) static void select_op_cells_to_modules(RTLIL::Design *design, RTLIL::Selection &lhs) { RTLIL::Selection new_sel(false); - for (auto &mod_it : design->modules_) - if (lhs.selected_module(mod_it.first)) - for (auto &cell_it : mod_it.second->cells_) - if (lhs.selected_member(mod_it.first, cell_it.first) && design->modules_.count(cell_it.second->type)) - new_sel.selected_modules.insert(cell_it.second->type); + for (auto mod : design->modules()) + if (lhs.selected_module(mod->name)) + for (auto cell : mod->cells()) + if (lhs.selected_member(mod->name, cell->name) && (design->module(cell->type) != nullptr)) + new_sel.selected_modules.insert(cell->type); lhs = new_sel; } static void select_op_module_to_cells(RTLIL::Design *design, RTLIL::Selection &lhs) { RTLIL::Selection new_sel(false); - for (auto &mod_it : design->modules_) - for (auto &cell_it : mod_it.second->cells_) - if (design->modules_.count(cell_it.second->type) && lhs.selected_whole_module(cell_it.second->type)) - new_sel.selected_members[mod_it.first].insert(cell_it.first); + for (auto mod : design->modules()) + for (auto cell : mod->cells()) + if ((design->module(cell->type) != nullptr) && lhs.selected_whole_module(cell->type)) + new_sel.selected_members[mod->name].insert(cell->name); lhs = new_sel; } @@ -268,23 +267,23 @@ static void select_op_fullmod(RTLIL::Design *design, RTLIL::Selection &lhs) static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs) { - for (auto &mod_it : design->modules_) + for (auto mod : design->modules()) { - if (lhs.selected_whole_module(mod_it.first)) + if (lhs.selected_whole_module(mod->name)) continue; - if (!lhs.selected_module(mod_it.first)) + if (!lhs.selected_module(mod->name)) continue; - SigMap sigmap(mod_it.second); + SigMap sigmap(mod); SigPool selected_bits; - for (auto &it : mod_it.second->wires_) - if (lhs.selected_member(mod_it.first, it.first)) - selected_bits.add(sigmap(it.second)); + for (auto wire : mod->wires()) + if (lhs.selected_member(mod->name, wire->name)) + selected_bits.add(sigmap(wire)); - for (auto &it : mod_it.second->wires_) - if (!lhs.selected_member(mod_it.first, it.first) && selected_bits.check_any(sigmap(it.second))) - lhs.selected_members[mod_it.first].insert(it.first); + for (auto wire : mod->wires()) + if (!lhs.selected_member(mod->name, wire->name) && selected_bits.check_any(sigmap(wire))) + lhs.selected_members[mod->name].insert(wire->name); } } @@ -323,8 +322,8 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R if (!rhs.full_selection && rhs.selected_modules.size() == 0 && rhs.selected_members.size() == 0) return; lhs.full_selection = false; - for (auto &it : design->modules_) - lhs.selected_modules.insert(it.first); + for (auto mod : design->modules()) + lhs.selected_modules.insert(mod->name); } for (auto &it : rhs.selected_modules) { @@ -334,19 +333,19 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R for (auto &it : rhs.selected_members) { - if (design->modules_.count(it.first) == 0) + if (design->module(it.first) == nullptr) continue; - RTLIL::Module *mod = design->modules_[it.first]; + RTLIL::Module *mod = design->module(it.first); if (lhs.selected_modules.count(mod->name) > 0) { - for (auto &it : mod->wires_) - lhs.selected_members[mod->name].insert(it.first); + for (auto wire : mod->wires()) + lhs.selected_members[mod->name].insert(wire->name); for (auto &it : mod->memories) lhs.selected_members[mod->name].insert(it.first); - for (auto &it : mod->cells_) - lhs.selected_members[mod->name].insert(it.first); + for (auto cell : mod->cells()) + lhs.selected_members[mod->name].insert(cell->name); for (auto &it : mod->processes) lhs.selected_members[mod->name].insert(it.first); lhs.selected_modules.erase(mod->name); @@ -367,8 +366,8 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co if (lhs.full_selection) { lhs.full_selection = false; - for (auto &it : design->modules_) - lhs.selected_modules.insert(it.first); + for (auto mod : design->modules()) + lhs.selected_modules.insert(mod->name); } std::vector<RTLIL::IdString> del_list; @@ -431,18 +430,17 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v { int sel_objects = 0; bool is_input, is_output; - for (auto &mod_it : design->modules_) + for (auto mod : design->modules()) { - if (lhs.selected_whole_module(mod_it.first) || !lhs.selected_module(mod_it.first)) + if (lhs.selected_whole_module(mod->name) || !lhs.selected_module(mod->name)) continue; - RTLIL::Module *mod = mod_it.second; std::set<RTLIL::Wire*> selected_wires; auto selected_members = lhs.selected_members[mod->name]; - for (auto &it : mod->wires_) - if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0) - selected_wires.insert(it.second); + for (auto wire : mod->wires()) + if (lhs.selected_member(mod->name, wire->name) && limits.count(wire->name) == 0) + selected_wires.insert(wire); for (auto &conn : mod->connections()) { @@ -450,7 +448,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector(); for (size_t i = 0; i < conn_lhs.size(); i++) { - if (conn_lhs[i].wire == NULL || conn_rhs[i].wire == NULL) + if (conn_lhs[i].wire == nullptr || conn_rhs[i].wire == nullptr) continue; if (mode != 'i' && selected_wires.count(conn_rhs[i].wire) && selected_members.count(conn_lhs[i].wire->name) == 0) lhs.selected_members[mod->name].insert(conn_lhs[i].wire->name), sel_objects++, max_objects--; @@ -459,15 +457,15 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v } } - for (auto &cell : mod->cells_) - for (auto &conn : cell.second->connections()) + for (auto cell : mod->cells()) + for (auto &conn : cell->connections()) { char last_mode = '-'; - if (eval_only && !yosys_celltypes.cell_evaluable(cell.second->type)) + if (eval_only && !yosys_celltypes.cell_evaluable(cell->type)) goto exclude_match; for (auto &rule : rules) { last_mode = rule.mode; - if (rule.cell_types.size() > 0 && rule.cell_types.count(cell.second->type) == 0) + if (rule.cell_types.size() > 0 && rule.cell_types.count(cell->type) == 0) continue; if (rule.port_names.size() > 0 && rule.port_names.count(conn.first) == 0) continue; @@ -479,14 +477,14 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v if (last_mode == '+') goto exclude_match; include_match: - is_input = mode == 'x' || ct.cell_input(cell.second->type, conn.first); - is_output = mode == 'x' || ct.cell_output(cell.second->type, conn.first); + is_input = mode == 'x' || ct.cell_input(cell->type, conn.first); + is_output = mode == 'x' || ct.cell_output(cell->type, conn.first); for (auto &chunk : conn.second.chunks()) - if (chunk.wire != NULL) { - if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && selected_members.count(cell.first) == 0) + if (chunk.wire != nullptr) { + if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && selected_members.count(cell->name) == 0) if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input)) - lhs.selected_members[mod->name].insert(cell.first), sel_objects++, max_objects--; - if (max_objects != 0 && selected_members.count(cell.first) > 0 && limits.count(cell.first) == 0 && selected_members.count(chunk.wire->name) == 0) + lhs.selected_members[mod->name].insert(cell->name), sel_objects++, max_objects--; + if (max_objects != 0 && selected_members.count(cell->name) > 0 && limits.count(cell->name) == 0 && selected_members.count(chunk.wire->name) == 0) if (mode == 'x' || (mode == 'i' && is_input) || (mode == 'o' && is_output)) lhs.selected_members[mod->name].insert(chunk.wire->name), sel_objects++, max_objects--; } @@ -627,9 +625,13 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se } } -static void select_stmt(RTLIL::Design *design, std::string arg) +static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_empty_warning = false) { std::string arg_mod, arg_memb; + std::unordered_map<std::string, bool> arg_mod_found; + std::unordered_map<std::string, bool> arg_memb_found; + auto isalpha = [](const char &x) { return ((x >= 'a' && x <= 'z') || (x >= 'A' && x <= 'Z')); }; + bool prefixed = GetSize(arg) >= 2 && isalpha(arg[0]) && arg[1] == ':'; if (arg.size() == 0) return; @@ -760,19 +762,21 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (!design->selected_active_module.empty()) { arg_mod = design->selected_active_module; arg_memb = arg; + if (!prefixed) arg_memb_found[arg_memb] = false; } else - if (GetSize(arg) >= 2 && arg[0] >= 'a' && arg[0] <= 'z' && arg[1] == ':') { + if (prefixed && arg[0] >= 'a' && arg[0] <= 'z') { arg_mod = "*", arg_memb = arg; } else { size_t pos = arg.find('/'); if (pos == std::string::npos) { - if (arg.find(':') == std::string::npos || arg.compare(0, 1, "A") == 0) - arg_mod = arg; - else - arg_mod = "*", arg_memb = arg; + arg_mod = arg; + if (!prefixed) arg_mod_found[arg_mod] = false; } else { arg_mod = arg.substr(0, pos); + if (!prefixed) arg_mod_found[arg_mod] = false; arg_memb = arg.substr(pos+1); + bool arg_memb_prefixed = GetSize(arg_memb) >= 2 && isalpha(arg_memb[0]) && arg_memb[1] == ':'; + if (!arg_memb_prefixed) arg_memb_found[arg_memb] = false; } } @@ -785,56 +789,61 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } sel.full_selection = false; - for (auto &mod_it : design->modules_) + for (auto mod : design->modules()) { if (arg_mod.compare(0, 2, "A:") == 0) { - if (!match_attr(mod_it.second->attributes, arg_mod.substr(2))) + if (!match_attr(mod->attributes, arg_mod.substr(2))) + continue; + } else + if (arg_mod.compare(0, 2, "N:") == 0) { + if (!match_ids(mod->name, arg_mod.substr(2))) continue; } else - if (!match_ids(mod_it.first, arg_mod)) + if (!match_ids(mod->name, arg_mod)) continue; + else + arg_mod_found[arg_mod] = true; if (arg_memb == "") { - sel.selected_modules.insert(mod_it.first); + sel.selected_modules.insert(mod->name); continue; } - RTLIL::Module *mod = mod_it.second; if (arg_memb.compare(0, 2, "w:") == 0) { - for (auto &it : mod->wires_) - if (match_ids(it.first, arg_memb.substr(2))) - sel.selected_members[mod->name].insert(it.first); + for (auto wire : mod->wires()) + if (match_ids(wire->name, arg_memb.substr(2))) + sel.selected_members[mod->name].insert(wire->name); } else if (arg_memb.compare(0, 2, "i:") == 0) { - for (auto &it : mod->wires_) - if (it.second->port_input && match_ids(it.first, arg_memb.substr(2))) - sel.selected_members[mod->name].insert(it.first); + for (auto wire : mod->wires()) + if (wire->port_input && match_ids(wire->name, arg_memb.substr(2))) + sel.selected_members[mod->name].insert(wire->name); } else if (arg_memb.compare(0, 2, "o:") == 0) { - for (auto &it : mod->wires_) - if (it.second->port_output && match_ids(it.first, arg_memb.substr(2))) - sel.selected_members[mod->name].insert(it.first); + for (auto wire : mod->wires()) + if (wire->port_output && match_ids(wire->name, arg_memb.substr(2))) + sel.selected_members[mod->name].insert(wire->name); } else if (arg_memb.compare(0, 2, "x:") == 0) { - for (auto &it : mod->wires_) - if ((it.second->port_input || it.second->port_output) && match_ids(it.first, arg_memb.substr(2))) - sel.selected_members[mod->name].insert(it.first); + for (auto wire : mod->wires()) + if ((wire->port_input || wire->port_output) && match_ids(wire->name, arg_memb.substr(2))) + sel.selected_members[mod->name].insert(wire->name); } else if (arg_memb.compare(0, 2, "s:") == 0) { size_t delim = arg_memb.substr(2).find(':'); if (delim == std::string::npos) { int width = atoi(arg_memb.substr(2).c_str()); - for (auto &it : mod->wires_) - if (it.second->width == width) - sel.selected_members[mod->name].insert(it.first); + for (auto wire : mod->wires()) + if (wire->width == width) + sel.selected_members[mod->name].insert(wire->name); } else { std::string min_str = arg_memb.substr(2, delim); std::string max_str = arg_memb.substr(2+delim+1); int min_width = min_str.empty() ? 0 : atoi(min_str.c_str()); int max_width = max_str.empty() ? -1 : atoi(max_str.c_str()); - for (auto &it : mod->wires_) - if (min_width <= it.second->width && (it.second->width <= max_width || max_width == -1)) - sel.selected_members[mod->name].insert(it.first); + for (auto wire : mod->wires()) + if (min_width <= wire->width && (wire->width <= max_width || max_width == -1)) + sel.selected_members[mod->name].insert(wire->name); } } else if (arg_memb.compare(0, 2, "m:") == 0) { @@ -842,15 +851,15 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else - if (arg_memb.compare(0, 2, "c:") ==0) { - for (auto &it : mod->cells_) - if (match_ids(it.first, arg_memb.substr(2))) - sel.selected_members[mod->name].insert(it.first); + if (arg_memb.compare(0, 2, "c:") == 0) { + for (auto cell : mod->cells()) + if (match_ids(cell->name, arg_memb.substr(2))) + sel.selected_members[mod->name].insert(cell->name); } else if (arg_memb.compare(0, 2, "t:") == 0) { - for (auto &it : mod->cells_) - if (match_ids(it.second->type, arg_memb.substr(2))) - sel.selected_members[mod->name].insert(it.first); + for (auto cell : mod->cells()) + if (match_ids(cell->type, arg_memb.substr(2))) + sel.selected_members[mod->name].insert(cell->name); } else if (arg_memb.compare(0, 2, "p:") == 0) { for (auto &it : mod->processes) @@ -858,62 +867,82 @@ static void select_stmt(RTLIL::Design *design, std::string arg) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.compare(0, 2, "a:") == 0) { - for (auto &it : mod->wires_) - if (match_attr(it.second->attributes, arg_memb.substr(2))) - sel.selected_members[mod->name].insert(it.first); + for (auto wire : mod->wires()) + if (match_attr(wire->attributes, arg_memb.substr(2))) + sel.selected_members[mod->name].insert(wire->name); for (auto &it : mod->memories) if (match_attr(it.second->attributes, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); - for (auto &it : mod->cells_) - if (match_attr(it.second->attributes, arg_memb.substr(2))) - sel.selected_members[mod->name].insert(it.first); + for (auto cell : mod->cells()) + if (match_attr(cell->attributes, arg_memb.substr(2))) + sel.selected_members[mod->name].insert(cell->name); for (auto &it : mod->processes) if (match_attr(it.second->attributes, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.compare(0, 2, "r:") == 0) { - for (auto &it : mod->cells_) - if (match_attr(it.second->parameters, arg_memb.substr(2))) - sel.selected_members[mod->name].insert(it.first); + for (auto cell : mod->cells()) + if (match_attr(cell->parameters, arg_memb.substr(2))) + sel.selected_members[mod->name].insert(cell->name); } else { + std::string orig_arg_memb = arg_memb; if (arg_memb.compare(0, 2, "n:") == 0) arg_memb = arg_memb.substr(2); - for (auto &it : mod->wires_) - if (match_ids(it.first, arg_memb)) - sel.selected_members[mod->name].insert(it.first); + for (auto wire : mod->wires()) + if (match_ids(wire->name, arg_memb)) { + sel.selected_members[mod->name].insert(wire->name); + arg_memb_found[orig_arg_memb] = true; + } for (auto &it : mod->memories) - if (match_ids(it.first, arg_memb)) - sel.selected_members[mod->name].insert(it.first); - for (auto &it : mod->cells_) - if (match_ids(it.first, arg_memb)) + if (match_ids(it.first, arg_memb)) { sel.selected_members[mod->name].insert(it.first); + arg_memb_found[orig_arg_memb] = true; + } + for (auto cell : mod->cells()) + if (match_ids(cell->name, arg_memb)) { + sel.selected_members[mod->name].insert(cell->name); + arg_memb_found[orig_arg_memb] = true; + } for (auto &it : mod->processes) - if (match_ids(it.first, arg_memb)) + if (match_ids(it.first, arg_memb)) { sel.selected_members[mod->name].insert(it.first); + arg_memb_found[orig_arg_memb] = true; + } } } select_filter_active_mod(design, work_stack.back()); + + for (auto &it : arg_mod_found) { + if (it.second == false && !disable_empty_warning) { + log_warning("Selection \"%s\" did not match any module.\n", it.first.c_str()); + } + } + for (auto &it : arg_memb_found) { + if (it.second == false && !disable_empty_warning) { + log_warning("Selection \"%s\" did not match any object.\n", it.first.c_str()); + } + } } static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::Selection *sel) { std::string desc = "Selection contains:\n"; - for (auto mod_it : design->modules_) + for (auto mod : design->modules()) { - if (sel->selected_module(mod_it.first)) { - for (auto &it : mod_it.second->wires_) - if (sel->selected_member(mod_it.first, it.first)) - desc += stringf("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); - for (auto &it : mod_it.second->memories) - if (sel->selected_member(mod_it.first, it.first)) - desc += stringf("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); - for (auto &it : mod_it.second->cells_) - if (sel->selected_member(mod_it.first, it.first)) - desc += stringf("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); - for (auto &it : mod_it.second->processes) - if (sel->selected_member(mod_it.first, it.first)) - desc += stringf("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); + if (sel->selected_module(mod->name)) { + for (auto wire : mod->wires()) + if (sel->selected_member(mod->name, wire->name)) + desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(wire->name)); + for (auto &it : mod->memories) + if (sel->selected_member(mod->name, it.first)) + desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it.first)); + for (auto cell : mod->cells()) + if (sel->selected_member(mod->name, cell->name)) + desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(cell->name)); + for (auto &it : mod->processes) + if (sel->selected_member(mod->name, it.first)) + desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it.first)); } } return desc; @@ -928,7 +957,7 @@ void handle_extra_select_args(Pass *pass, vector<string> args, size_t argidx, si work_stack.clear(); for (; argidx < args_size; argidx++) { if (args[argidx].compare(0, 1, "-") == 0) { - if (pass != NULL) + if (pass != nullptr) pass->cmd_error(args, argidx, "Unexpected option in selection arguments."); else log_cmd_error("Unexpected option in selection arguments."); @@ -1077,6 +1106,10 @@ struct SelectPass : public Pass { log(" all modules with an attribute matching the given pattern\n"); log(" in addition to = also <, <=, >=, and > are supported\n"); log("\n"); + log(" N:<pattern>\n"); + log(" all modules with a name matching the given pattern\n"); + log(" (i.e. 'N:' is optional as it is the default matching rule)\n"); + log("\n"); log("An <obj_pattern> can be an object name, wildcard expression, or one of\n"); log("the following:\n"); log("\n"); @@ -1267,7 +1300,7 @@ struct SelectPass : public Pass { } if (arg == "-module" && argidx+1 < args.size()) { RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]); - if (design->modules_.count(mod_name) == 0) + if (design->module(mod_name) == nullptr) log_cmd_error("No such module: %s\n", id2cstr(mod_name)); design->selected_active_module = mod_name.str(); got_module = true; @@ -1279,7 +1312,8 @@ struct SelectPass : public Pass { } if (arg.size() > 0 && arg[0] == '-') log_cmd_error("Unknown option %s.\n", arg.c_str()); - select_stmt(design, arg); + bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_count != -1) || (assert_max != -1) || (assert_min != -1); + select_stmt(design, arg, disable_empty_warning); sel_str += " " + arg; } @@ -1353,41 +1387,41 @@ struct SelectPass : public Pass { if (list_mode || count_mode || !write_file.empty()) { - #define LOG_OBJECT(...) { if (list_mode) log(__VA_ARGS__); if (f != NULL) fprintf(f, __VA_ARGS__); total_count++; } + #define LOG_OBJECT(...) { if (list_mode) log(__VA_ARGS__); if (f != nullptr) fprintf(f, __VA_ARGS__); total_count++; } int total_count = 0; - FILE *f = NULL; + FILE *f = nullptr; if (!write_file.empty()) { f = fopen(write_file.c_str(), "w"); yosys_output_files.insert(write_file); - if (f == NULL) + if (f == nullptr) log_error("Can't open '%s' for writing: %s\n", write_file.c_str(), strerror(errno)); } RTLIL::Selection *sel = &design->selection_stack.back(); if (work_stack.size() > 0) sel = &work_stack.back(); sel->optimize(design); - for (auto mod_it : design->modules_) + for (auto mod : design->modules()) { - if (sel->selected_whole_module(mod_it.first) && list_mode) - log("%s\n", id2cstr(mod_it.first)); - if (sel->selected_module(mod_it.first)) { - for (auto &it : mod_it.second->wires_) - if (sel->selected_member(mod_it.first, it.first)) - LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)) - for (auto &it : mod_it.second->memories) - if (sel->selected_member(mod_it.first, it.first)) - LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)) - for (auto &it : mod_it.second->cells_) - if (sel->selected_member(mod_it.first, it.first)) - LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)) - for (auto &it : mod_it.second->processes) - if (sel->selected_member(mod_it.first, it.first)) - LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)) + if (sel->selected_whole_module(mod->name) && list_mode) + log("%s\n", id2cstr(mod->name)); + if (sel->selected_module(mod->name)) { + for (auto wire : mod->wires()) + if (sel->selected_member(mod->name, wire->name)) + LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(wire->name)) + for (auto &it : mod->memories) + if (sel->selected_member(mod->name, it.first)) + LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it.first)) + for (auto cell : mod->cells()) + if (sel->selected_member(mod->name, cell->name)) + LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(cell->name)) + for (auto &it : mod->processes) + if (sel->selected_member(mod->name, it.first)) + LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it.first)) } } if (count_mode) log("%d objects.\n", total_count); - if (f != NULL) + if (f != nullptr) fclose(f); #undef LOG_OBJECT return; @@ -1448,19 +1482,19 @@ struct SelectPass : public Pass { log_cmd_error("No selection to check.\n"); RTLIL::Selection *sel = &work_stack.back(); sel->optimize(design); - for (auto mod_it : design->modules_) - if (sel->selected_module(mod_it.first)) { - for (auto &it : mod_it.second->wires_) - if (sel->selected_member(mod_it.first, it.first)) + for (auto mod : design->modules()) + if (sel->selected_module(mod->name)) { + for (auto wire : mod->wires()) + if (sel->selected_member(mod->name, wire->name)) total_count++; - for (auto &it : mod_it.second->memories) - if (sel->selected_member(mod_it.first, it.first)) + for (auto &it : mod->memories) + if (sel->selected_member(mod->name, it.first)) total_count++; - for (auto &it : mod_it.second->cells_) - if (sel->selected_member(mod_it.first, it.first)) + for (auto cell : mod->cells()) + if (sel->selected_member(mod->name, cell->name)) total_count++; - for (auto &it : mod_it.second->processes) - if (sel->selected_member(mod_it.first, it.first)) + for (auto &it : mod->processes) + if (sel->selected_member(mod->name, it.first)) total_count++; } if (assert_count >= 0 && assert_count != total_count) @@ -1581,15 +1615,13 @@ struct CdPass : public Pass { std::string modname = RTLIL::escape_id(args[1]); - if (design->modules_.count(modname) == 0 && !design->selected_active_module.empty()) { - RTLIL::Module *module = NULL; - if (design->modules_.count(design->selected_active_module) > 0) - module = design->modules_.at(design->selected_active_module); - if (module != NULL && module->cells_.count(modname) > 0) - modname = module->cells_.at(modname)->type.str(); + if (design->module(modname) == nullptr && !design->selected_active_module.empty()) { + RTLIL::Module *module = design->module(design->selected_active_module); + if (module != nullptr && module->cell(modname) != nullptr) + modname = module->cell(modname)->type.str(); } - if (design->modules_.count(modname) > 0) { + if (design->module(modname) != nullptr) { design->selected_active_module = modname; design->selection_stack.back() = RTLIL::Selection(); select_filter_active_mod(design, design->selection_stack.back()); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index eeef24bde..e0d428811 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -668,6 +668,10 @@ struct ShowPass : public Pass { log(" -notitle\n"); log(" do not add the module name as graph title to the dot file\n"); log("\n"); + log(" -nobg\n"); + log(" don't run viewer in the background, IE wait for the viewer tool to\n"); + log(" exit before returning\n"); + log("\n"); log("When no <format> is specified, 'dot' is used. When no <format> and <viewer> is\n"); log("specified, 'xdot' is used to display the schematic (POSIX systems only).\n"); log("\n"); @@ -706,6 +710,7 @@ struct ShowPass : public Pass { bool flag_abbreviate = true; bool flag_notitle = false; bool custom_prefix = false; + std::string background = "&"; RTLIL::IdString colorattr; size_t argidx; @@ -787,6 +792,10 @@ struct ShowPass : public Pass { flag_notitle = true; continue; } + if (arg == "-nobg") { + background= ""; + continue; + } break; } extra_args(args, argidx, design); @@ -859,21 +868,19 @@ struct ShowPass : public Pass { // system()/cmd.exe does not understand single quotes nor // background tasks on Windows. So we have to pause yosys // until the viewer exits. - #define VIEW_CMD "%s \"%s\"" + std::string cmd = stringf("%s \"%s\"", viewer_exe.c_str(), out_file.c_str()); #else - #define VIEW_CMD "%s '%s' &" + std::string cmd = stringf("%s '%s' %s", viewer_exe.c_str(), out_file.c_str(), background.c_str()); #endif - std::string cmd = stringf(VIEW_CMD, viewer_exe.c_str(), out_file.c_str()); - #undef VIEW_CMD log("Exec: %s\n", cmd.c_str()); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); } else if (format.empty()) { #ifdef __APPLE__ - std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' &", getuid(), dot_file.c_str(), dot_file.c_str()); + std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str()); #else - std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' &", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str()); + std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str()); #endif log("Exec: %s\n", cmd.c_str()); if (run_command(cmd) != 0) diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index a85c3bec0..0f7b4d106 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -422,11 +422,7 @@ struct FsmExtractPass : public Pass { log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n"); extra_args(args, 1, design); - CellTypes ct; - ct.setup_internals(); - ct.setup_internals_mem(); - ct.setup_stdcells(); - ct.setup_stdcells_mem(); + CellTypes ct(design); for (auto &mod_it : design->modules_) { diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index ec242aa1f..3b4f33a60 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -20,6 +20,7 @@ #include "kernel/register.h" #include "kernel/celltypes.h" #include "kernel/log.h" +#include "kernel/sigtools.h" #include <stdlib.h> #include <stdio.h> #include <set> @@ -32,49 +33,56 @@ struct SubmodWorker CellTypes ct; RTLIL::Design *design; RTLIL::Module *module; + SigMap sigmap; bool copy_mode; + bool hidden_mode; std::string opt_name; struct SubModule { std::string name, full_name; - std::set<RTLIL::Cell*> cells; + pool<RTLIL::Cell*> cells; }; std::map<std::string, SubModule> submodules; struct wire_flags_t { RTLIL::Wire *new_wire; - bool is_int_driven, is_int_used, is_ext_driven, is_ext_used; - wire_flags_t() : new_wire(NULL), is_int_driven(false), is_int_used(false), is_ext_driven(false), is_ext_used(false) { } + RTLIL::Const is_int_driven; + bool is_int_used, is_ext_driven, is_ext_used; + wire_flags_t(RTLIL::Wire* wire) : new_wire(NULL), is_int_driven(State::S0, GetSize(wire)), is_int_used(false), is_ext_driven(false), is_ext_used(false) { } }; std::map<RTLIL::Wire*, wire_flags_t> wire_flags; bool flag_found_something; - void flag_wire(RTLIL::Wire *wire, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used) + void flag_wire(RTLIL::Wire *wire, bool create, bool set_int_used, bool set_ext_driven, bool set_ext_used) { if (wire_flags.count(wire) == 0) { if (!create) return; - wire_flags[wire] = wire_flags_t(); + wire_flags.emplace(wire, wire); } - if (set_int_driven) - wire_flags[wire].is_int_driven = true; if (set_int_used) - wire_flags[wire].is_int_used = true; + wire_flags.at(wire).is_int_used = true; if (set_ext_driven) - wire_flags[wire].is_ext_driven = true; + wire_flags.at(wire).is_ext_driven = true; if (set_ext_used) - wire_flags[wire].is_ext_used = true; + wire_flags.at(wire).is_ext_used = true; flag_found_something = true; } void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used) { for (auto &c : sig.chunks()) - if (c.wire != NULL) - flag_wire(c.wire, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used); + if (c.wire != NULL) { + flag_wire(c.wire, create, set_int_used, set_ext_driven, set_ext_used); + if (set_int_driven) + for (int i = c.offset; i < c.offset+c.width; i++) { + wire_flags.at(c.wire).is_int_driven[i] = State::S1; + flag_found_something = true; + } + } } void handle_submodule(SubModule &submod) @@ -127,27 +135,39 @@ struct SubmodWorker flags.is_ext_driven = true; if (wire->port_output) flags.is_ext_used = true; + else { + auto sig = sigmap(wire); + for (auto c : sig.chunks()) + if (c.wire && c.wire->port_output) { + flags.is_ext_used = true; + break; + } + } bool new_wire_port_input = false; bool new_wire_port_output = false; - if (flags.is_int_driven && flags.is_ext_used) + if (!flags.is_int_driven.is_fully_zero() && flags.is_ext_used) new_wire_port_output = true; if (flags.is_ext_driven && flags.is_int_used) new_wire_port_input = true; - if (flags.is_int_driven && flags.is_ext_driven) + if (!flags.is_int_driven.is_fully_zero() && flags.is_ext_driven) new_wire_port_input = true, new_wire_port_output = true; std::string new_wire_name = wire->name.str(); if (new_wire_port_input || new_wire_port_output) { - while (new_wire_name[0] == '$') { - std::string next_wire_name = stringf("\\n%d", auto_name_counter++); - if (all_wire_names.count(next_wire_name) == 0) { - all_wire_names.insert(next_wire_name); - new_wire_name = next_wire_name; + if (new_wire_name[0] == '$') + while (1) { + std::string next_wire_name = stringf("%s\\n%d", hidden_mode ? "$submod" : "", auto_name_counter++); + if (all_wire_names.count(next_wire_name) == 0) { + all_wire_names.insert(next_wire_name); + new_wire_name = next_wire_name; + break; + } } - } + else if (hidden_mode) + new_wire_name = stringf("$submod%s", new_wire_name.c_str()); } RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name, wire->width); @@ -155,6 +175,22 @@ struct SubmodWorker new_wire->port_output = new_wire_port_output; new_wire->start_offset = wire->start_offset; new_wire->attributes = wire->attributes; + if (!flags.is_int_driven.is_fully_zero()) { + new_wire->attributes.erase(ID(init)); + auto sig = sigmap(wire); + for (int i = 0; i < GetSize(sig); i++) { + if (flags.is_int_driven[i] == State::S0) + continue; + if (!sig[i].wire) + continue; + auto it = sig[i].wire->attributes.find(ID(init)); + if (it != sig[i].wire->attributes.end()) { + auto jt = new_wire->attributes.insert(std::make_pair(ID(init), Const(State::Sx, GetSize(sig)))).first; + jt->second[i] = it->second[sig[i].offset]; + it->second[sig[i].offset] = State::Sx; + } + } + } if (new_wire->port_input && new_wire->port_output) log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str()); @@ -177,7 +213,7 @@ struct SubmodWorker for (auto &bit : conn.second) if (bit.wire != NULL) { log_assert(wire_flags.count(bit.wire) > 0); - bit.wire = wire_flags[bit.wire].new_wire; + bit.wire = wire_flags.at(bit.wire).new_wire; } log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str()); if (!copy_mode) @@ -189,16 +225,27 @@ struct SubmodWorker RTLIL::Cell *new_cell = module->addCell(submod.full_name, submod.full_name); for (auto &it : wire_flags) { - RTLIL::Wire *old_wire = it.first; + RTLIL::SigSpec old_sig = sigmap(it.first); RTLIL::Wire *new_wire = it.second.new_wire; - if (new_wire->port_id > 0) - new_cell->setPort(new_wire->name, RTLIL::SigSpec(old_wire)); + if (new_wire->port_id > 0) { + if (new_wire->port_output) + for (int i = 0; i < GetSize(old_sig); i++) { + auto &b = old_sig[i]; + // Prevents "ERROR: Mismatch in directionality ..." when flattening + if (!b.wire) + b = module->addWire(NEW_ID); + // Prevents "Warning: multiple conflicting drivers ..." + else if (!it.second.is_int_driven[i]) + b = module->addWire(NEW_ID); + } + new_cell->setPort(new_wire->name, old_sig); + } } } } - SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, std::string opt_name = std::string()) : - design(design), module(module), copy_mode(copy_mode), opt_name(opt_name) + SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, bool hidden_mode = false, std::string opt_name = std::string()) : + design(design), module(module), sigmap(module), copy_mode(copy_mode), hidden_mode(hidden_mode), opt_name(opt_name) { if (!design->selected_whole_module(module->name) && opt_name.empty()) return; @@ -219,6 +266,12 @@ struct SubmodWorker ct.setup_stdcells_mem(); ct.setup_design(design); + for (auto port : module->ports) { + auto wire = module->wire(port); + if (wire->port_output) + sigmap.add(wire); + } + if (opt_name.empty()) { for (auto &it : module->wires_) @@ -273,7 +326,7 @@ struct SubmodPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" submod [-copy] [selection]\n"); + log(" submod [options] [selection]\n"); log("\n"); log("This pass identifies all cells with the 'submod' attribute and moves them to\n"); log("a newly created module. The value of the attribute is used as name for the\n"); @@ -285,16 +338,20 @@ struct SubmodPass : public Pass { log("This pass only operates on completely selected modules with no processes\n"); log("or memories.\n"); log("\n"); + log(" -copy\n"); + log(" by default the cells are 'moved' from the source module and the source\n"); + log(" module will use an instance of the new module after this command is\n"); + log(" finished. call with -copy to not modify the source module.\n"); log("\n"); - log(" submod -name <name> [-copy] [selection]\n"); - log("\n"); - log("As above, but don't use the 'submod' attribute but instead use the selection.\n"); - log("Only objects from one module might be selected. The value of the -name option\n"); - log("is used as the value of the 'submod' attribute above.\n"); + log(" -name <name>\n"); + log(" don't use the 'submod' attribute but instead use the selection. only\n"); + log(" objects from one module might be selected. the value of the -name option\n"); + log(" is used as the value of the 'submod' attribute instead.\n"); log("\n"); - log("By default the cells are 'moved' from the source module and the source module\n"); - log("will use an instance of the new module after this command is finished. Call\n"); - log("with -copy to not modify the source module.\n"); + log(" -hidden\n"); + log(" instead of creating submodule ports with public names, create ports with\n"); + log(" private names so that a subsequent 'flatten; clean' call will restore the\n"); + log(" original module with original public names.\n"); log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE @@ -304,6 +361,7 @@ struct SubmodPass : public Pass { std::string opt_name; bool copy_mode = false; + bool hidden_mode = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -315,6 +373,10 @@ struct SubmodPass : public Pass { copy_mode = true; continue; } + if (args[argidx] == "-hidden") { + hidden_mode = true; + continue; + } break; } extra_args(args, argidx, design); @@ -335,7 +397,7 @@ struct SubmodPass : public Pass { queued_modules.push_back(mod_it.first); for (auto &modname : queued_modules) if (design->modules_.count(modname) != 0) { - SubmodWorker worker(design, design->modules_[modname], copy_mode); + SubmodWorker worker(design, design->modules_[modname], copy_mode, hidden_mode); handled_modules.insert(modname); did_something = true; } @@ -358,7 +420,7 @@ struct SubmodPass : public Pass { else { Pass::call_on_module(design, module, "opt_clean"); log_header(design, "Continuing SUBMOD pass.\n"); - SubmodWorker worker(design, module, copy_mode, opt_name); + SubmodWorker worker(design, module, copy_mode, hidden_mode, opt_name); } } diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 2f69b3d4c..cac265a52 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -53,18 +53,24 @@ struct keep_cache_t cache[module] = true; if (!module->get_bool_attribute(ID::keep)) { - bool found_keep = false; - for (auto cell : module->cells()) - if (query(cell)) found_keep = true; - cache[module] = found_keep; + bool found_keep = false; + for (auto cell : module->cells()) + if (query(cell, true /* ignore_specify */)) { + found_keep = true; + break; + } + cache[module] = found_keep; } return cache[module]; } - bool query(Cell *cell) + bool query(Cell *cell, bool ignore_specify = false) { - if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($specify2), ID($specify3), ID($specrule))) + if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) + return true; + + if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule))) return true; if (cell->has_keep_attr()) diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 49ef40061..742433935 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -66,50 +66,48 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: RTLIL::IdString gate_name = RTLIL::escape_id(args[argidx++]); RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]); - if (design->modules_.count(gold_name) == 0) + if (design->module(gold_name) == nullptr) log_cmd_error("Can't find gold module %s!\n", gold_name.c_str()); - if (design->modules_.count(gate_name) == 0) + if (design->module(gate_name) == nullptr) log_cmd_error("Can't find gate module %s!\n", gate_name.c_str()); - if (design->modules_.count(miter_name) != 0) + if (design->module(miter_name) != nullptr) log_cmd_error("There is already a module %s!\n", miter_name.c_str()); - RTLIL::Module *gold_module = design->modules_.at(gold_name); - RTLIL::Module *gate_module = design->modules_.at(gate_name); + RTLIL::Module *gold_module = design->module(gold_name); + RTLIL::Module *gate_module = design->module(gate_name); - for (auto &it : gold_module->wires_) { - RTLIL::Wire *w1 = it.second, *w2; - if (w1->port_id == 0) + for (auto gold_wire : gold_module->wires()) { + if (gold_wire->port_id == 0) continue; - if (gate_module->wires_.count(it.second->name) == 0) + RTLIL::Wire *gate_wire = gate_module->wire(gold_wire->name); + if (gate_wire == nullptr) goto match_gold_port_error; - w2 = gate_module->wires_.at(it.second->name); - if (w1->port_input != w2->port_input) + if (gold_wire->port_input != gate_wire->port_input) goto match_gold_port_error; - if (w1->port_output != w2->port_output) + if (gold_wire->port_output != gate_wire->port_output) goto match_gold_port_error; - if (w1->width != w2->width) + if (gold_wire->width != gate_wire->width) goto match_gold_port_error; continue; match_gold_port_error: - log_cmd_error("No matching port in gate module was found for %s!\n", it.second->name.c_str()); + log_cmd_error("No matching port in gate module was found for %s!\n", gold_wire->name.c_str()); } - for (auto &it : gate_module->wires_) { - RTLIL::Wire *w1 = it.second, *w2; - if (w1->port_id == 0) + for (auto gate_wire : gate_module->wires()) { + if (gate_wire->port_id == 0) continue; - if (gold_module->wires_.count(it.second->name) == 0) + RTLIL::Wire *gold_wire = gold_module->wire(gate_wire->name); + if (gold_wire == nullptr) goto match_gate_port_error; - w2 = gold_module->wires_.at(it.second->name); - if (w1->port_input != w2->port_input) + if (gate_wire->port_input != gold_wire->port_input) goto match_gate_port_error; - if (w1->port_output != w2->port_output) + if (gate_wire->port_output != gold_wire->port_output) goto match_gate_port_error; - if (w1->width != w2->width) + if (gate_wire->width != gold_wire->width) goto match_gate_port_error; continue; match_gate_port_error: - log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str()); + log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name.c_str()); } log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name)); @@ -123,73 +121,71 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: RTLIL::SigSpec all_conditions; - for (auto &it : gold_module->wires_) + for (auto gold_wire : gold_module->wires()) { - RTLIL::Wire *w1 = it.second; - - if (w1->port_input) + if (gold_wire->port_input) { - RTLIL::Wire *w2 = miter_module->addWire("\\in_" + RTLIL::unescape_id(w1->name), w1->width); - w2->port_input = true; + RTLIL::Wire *w = miter_module->addWire("\\in_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); + w->port_input = true; - gold_cell->setPort(w1->name, w2); - gate_cell->setPort(w1->name, w2); + gold_cell->setPort(gold_wire->name, w); + gate_cell->setPort(gold_wire->name, w); } - if (w1->port_output) + if (gold_wire->port_output) { - RTLIL::Wire *w2_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(w1->name), w1->width); - w2_gold->port_output = flag_make_outputs; + RTLIL::Wire *w_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); + w_gold->port_output = flag_make_outputs; - RTLIL::Wire *w2_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(w1->name), w1->width); - w2_gate->port_output = flag_make_outputs; + RTLIL::Wire *w_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); + w_gate->port_output = flag_make_outputs; - gold_cell->setPort(w1->name, w2_gold); - gate_cell->setPort(w1->name, w2_gate); + gold_cell->setPort(gold_wire->name, w_gold); + gate_cell->setPort(gold_wire->name, w_gate); RTLIL::SigSpec this_condition; if (flag_ignore_gold_x) { - RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width); - for (int i = 0; i < w2_gold->width; i++) { + RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w_gold->width); + for (int i = 0; i < w_gold->width; i++) { RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, "$eqx"); eqx_cell->parameters["\\A_WIDTH"] = 1; eqx_cell->parameters["\\B_WIDTH"] = 1; eqx_cell->parameters["\\Y_WIDTH"] = 1; eqx_cell->parameters["\\A_SIGNED"] = 0; eqx_cell->parameters["\\B_SIGNED"] = 0; - eqx_cell->setPort("\\A", RTLIL::SigSpec(w2_gold, i)); + eqx_cell->setPort("\\A", RTLIL::SigSpec(w_gold, i)); eqx_cell->setPort("\\B", RTLIL::State::Sx); eqx_cell->setPort("\\Y", gold_x.extract(i, 1)); } - RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width); - RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width); + RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width); + RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w_gate->width); RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, "$or"); - or_gold_cell->parameters["\\A_WIDTH"] = w2_gold->width; - or_gold_cell->parameters["\\B_WIDTH"] = w2_gold->width; - or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width; + or_gold_cell->parameters["\\A_WIDTH"] = w_gold->width; + or_gold_cell->parameters["\\B_WIDTH"] = w_gold->width; + or_gold_cell->parameters["\\Y_WIDTH"] = w_gold->width; or_gold_cell->parameters["\\A_SIGNED"] = 0; or_gold_cell->parameters["\\B_SIGNED"] = 0; - or_gold_cell->setPort("\\A", w2_gold); + or_gold_cell->setPort("\\A", w_gold); or_gold_cell->setPort("\\B", gold_x); or_gold_cell->setPort("\\Y", gold_masked); RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or"); - or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width; - or_gate_cell->parameters["\\B_WIDTH"] = w2_gate->width; - or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width; + or_gate_cell->parameters["\\A_WIDTH"] = w_gate->width; + or_gate_cell->parameters["\\B_WIDTH"] = w_gate->width; + or_gate_cell->parameters["\\Y_WIDTH"] = w_gate->width; or_gate_cell->parameters["\\A_SIGNED"] = 0; or_gate_cell->parameters["\\B_SIGNED"] = 0; - or_gate_cell->setPort("\\A", w2_gate); + or_gate_cell->setPort("\\A", w_gate); or_gate_cell->setPort("\\B", gold_x); or_gate_cell->setPort("\\Y", gate_masked); RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx"); - eq_cell->parameters["\\A_WIDTH"] = w2_gold->width; - eq_cell->parameters["\\B_WIDTH"] = w2_gate->width; + eq_cell->parameters["\\A_WIDTH"] = w_gold->width; + eq_cell->parameters["\\B_WIDTH"] = w_gate->width; eq_cell->parameters["\\Y_WIDTH"] = 1; eq_cell->parameters["\\A_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0; @@ -201,20 +197,20 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: else { RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx"); - eq_cell->parameters["\\A_WIDTH"] = w2_gold->width; - eq_cell->parameters["\\B_WIDTH"] = w2_gate->width; + eq_cell->parameters["\\A_WIDTH"] = w_gold->width; + eq_cell->parameters["\\B_WIDTH"] = w_gate->width; eq_cell->parameters["\\Y_WIDTH"] = 1; eq_cell->parameters["\\A_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->setPort("\\A", w2_gold); - eq_cell->setPort("\\B", w2_gate); + eq_cell->setPort("\\A", w_gold); + eq_cell->setPort("\\B", w_gate); eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID)); this_condition = eq_cell->getPort("\\Y"); } if (flag_make_outcmp) { - RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(w1->name)); + RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(gold_wire->name)); w_cmp->port_output = true; miter_module->connect(RTLIL::SigSig(w_cmp, this_condition)); } @@ -285,9 +281,9 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL IdString module_name = RTLIL::escape_id(args[argidx++]); IdString miter_name = argidx < args.size() ? RTLIL::escape_id(args[argidx++]) : ""; - if (design->modules_.count(module_name) == 0) + if (design->module(module_name) == nullptr) log_cmd_error("Can't find module %s!\n", module_name.c_str()); - if (!miter_name.empty() && design->modules_.count(miter_name) != 0) + if (!miter_name.empty() && design->module(miter_name) != nullptr) log_cmd_error("There is already a module %s!\n", miter_name.c_str()); Module *module = design->module(module_name); diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 581652a41..e6c189c3e 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1553,6 +1553,11 @@ struct AbcPass : public Pass { show_tempdir = design->scratchpad_get_bool("abc.showtmp", show_tempdir); markgroups = design->scratchpad_get_bool("abc.markgroups", markgroups); + if (design->scratchpad_get_bool("abc.debug")) { + cleanup = false; + show_tempdir = true; + } + size_t argidx, g_argidx; bool g_arg_from_cmd = false; char pwd [PATH_MAX]; diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 5ae2fb22a..212e0692d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -145,6 +145,11 @@ struct Abc9Pass : public ScriptPass log(" generate netlist using luts. Use the specified costs for luts with 1,\n"); log(" 2, 3, .. inputs.\n"); log("\n"); + log(" -maxlut <width>\n"); + log(" when auto-generating the lut library, discard all luts equal to or\n"); + log(" greater than this size (applicable when neither -lut nor -luts is\n"); + log(" specified).\n"); + log("\n"); log(" -dff\n"); log(" also pass $_ABC9_FF_ cells through to ABC. modules with many clock\n"); log(" domains are marked as such and automatically partitioned by ABC.\n"); @@ -175,6 +180,8 @@ struct Abc9Pass : public ScriptPass std::stringstream exe_cmd; bool dff_mode, cleanup; + bool lut_mode; + int maxlut; std::string box_file; void clear_flags() YS_OVERRIDE @@ -183,7 +190,9 @@ struct Abc9Pass : public ScriptPass exe_cmd << "abc9_exe"; dff_mode = false; cleanup = true; - box_file.clear(); + lut_mode = false; + maxlut = 0; + box_file = ""; } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE @@ -204,9 +213,11 @@ struct Abc9Pass : public ScriptPass for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if ((arg == "-exe" || arg == "-script" || arg == "-D" || - /* arg == "-S" || */ arg == "-lut" || arg == "-luts" || + /*arg == "-S" ||*/ arg == "-lut" || arg == "-luts" || /*arg == "-box" ||*/ arg == "-W") && argidx+1 < args.size()) { + if (arg == "-lut" || arg == "-luts") + lut_mode = true; exe_cmd << " " << arg << " " << args[++argidx]; continue; } @@ -228,6 +239,10 @@ struct Abc9Pass : public ScriptPass box_file = args[++argidx]; continue; } + if (arg == "-maxlut" && argidx+1 < args.size()) { + maxlut = atoi(args[++argidx].c_str()); + continue; + } if (arg == "-run" && argidx+1 < args.size()) { size_t pos = args[argidx+1].find(':'); if (pos == std::string::npos) @@ -240,6 +255,9 @@ struct Abc9Pass : public ScriptPass } extra_args(args, argidx, design); + if (maxlut && lut_mode) + log_cmd_error("abc9 '-maxlut' option only applicable without '-lut' nor '-luts'.\n"); + log_assert(design); if (design->selected_modules().empty()) { log_warning("No modules selected for ABC9 techmapping.\n"); @@ -263,6 +281,14 @@ struct Abc9Pass : public ScriptPass run("abc9_ops -mark_scc -prep_delays -prep_xaiger [-dff]", "(option for -dff)"); else run("abc9_ops -mark_scc -prep_delays -prep_xaiger" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)"); + if (help_mode) + run("abc9_ops -prep_lut <maxlut>", "(skip if -lut or -luts)"); + else if (!lut_mode) + run(stringf("abc9_ops -prep_lut %d", maxlut)); + if (help_mode) + run("abc9_ops -prep_box [-dff]", "(skip if -box)"); + else if (box_file.empty()) + run(stringf("abc9_ops -prep_box %s", dff_mode ? "-dff" : "")); run("select -set abc9_holes A:abc9_holes"); run("flatten -wb @abc9_holes"); run("techmap @abc9_holes"); @@ -276,9 +302,10 @@ struct Abc9Pass : public ScriptPass if (check_label("map")) { if (help_mode) { run("foreach module in selection"); - run(" abc9_ops -write_box [<value from -box>|(null)] <abc-temp-dir>/input.box"); + run(" abc9_ops -write_lut <abc-temp-dir>/input.lut", "(skip if '-lut' or '-luts')"); + run(" abc9_ops -write_box <abc-temp-dir>/input.box"); run(" write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig"); - run(" abc9_exe [options] -cwd <abc-temp-dir> -box <abc-temp-dir>/input.box"); + run(" abc9_exe [options] -cwd <abc-temp-dir> [-lut <abc-temp-dir>/input.lut] -box <abc-temp-dir>/input.box"); run(" read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig"); run(" abc9_ops -reintegrate"); } @@ -304,11 +331,10 @@ struct Abc9Pass : public ScriptPass tempdir_name[0] = tempdir_name[4] = '_'; tempdir_name = make_temp_dir(tempdir_name); - if (box_file.empty()) - run(stringf("abc9_ops -write_box (null) %s/input.box", tempdir_name.c_str())); - else - run(stringf("abc9_ops -write_box %s %s/input.box", box_file.c_str(), tempdir_name.c_str())); - run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str())); + if (!lut_mode) + run_nocheck(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str())); + run_nocheck(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str())); + run_nocheck(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str())); int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs"); @@ -319,9 +345,14 @@ struct Abc9Pass : public ScriptPass active_design->scratchpad_get_int("write_xaiger.num_inputs"), num_outputs); if (num_outputs) { - run(stringf("%s -cwd %s -box %s/input.box", exe_cmd.str().c_str(), tempdir_name.c_str(), tempdir_name.c_str())); - run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str())); - run("abc9_ops -reintegrate"); + std::string abc9_exe_cmd; + abc9_exe_cmd += stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str()); + if (!lut_mode) + abc9_exe_cmd += stringf(" -lut %s/input.lut", tempdir_name.c_str()); + abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name.c_str()); + run_nocheck(abc9_exe_cmd); + run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str())); + run_nocheck("abc9_ops -reintegrate"); } else log("Don't call ABC as there is nothing to map.\n"); @@ -330,7 +361,7 @@ struct Abc9Pass : public ScriptPass log("Removing temp directory.\n"); remove_directory(tempdir_name); } - + mod->check(); active_design->selection().selected_modules.clear(); log_pop(); } diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index 71221951c..898285c69 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -362,7 +362,7 @@ struct Abc9ExePass : public Pass { } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { - log_header(design, "Executing ABC9_MAP pass (technology mapping using ABC9).\n"); + log_header(design, "Executing ABC9_EXE pass (technology mapping using ABC9).\n"); #ifdef ABCEXTERNAL std::string exe_file = ABCEXTERNAL; @@ -471,7 +471,7 @@ struct Abc9ExePass : public Pass { // handle -lut / -luts args if (!lut_arg.empty()) { string arg = lut_arg; - if (arg.find_first_not_of("0123456789:") == std::string::npos) { + if (arg.find_first_not_of("0123456789:,") == std::string::npos) { size_t pos = arg.find_first_of(':'); int lut_mode = 0, lut_mode2 = 0; if (pos != string::npos) { diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 7071f0de4..e1baf4e3d 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -22,9 +22,7 @@ #include "kernel/sigtools.h" #include "kernel/utils.h" #include "kernel/celltypes.h" - -#define ABC9_FLOPS_BASE_ID 8000 -#define ABC9_DELAY_BASE_ID 9000 +#include "kernel/timinginfo.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -73,54 +71,6 @@ void check(RTLIL::Design *design) carry_out = port_name; } } - - auto it = w->attributes.find("\\abc9_arrival"); - if (it != w->attributes.end()) { - int count = 0; - if (it->second.flags == 0) { - if (it->second.as_int() < 0) - log_error("%s.%s has negative arrival value %d!\n", log_id(m), log_id(port_name), - it->second.as_int()); - count++; - } - else - for (const auto &tok : split_tokens(it->second.decode_string())) { - if (tok.find_first_not_of("0123456789") != std::string::npos) - log_error("%s.%s has non-integer arrival value '%s'!\n", log_id(m), log_id(port_name), - tok.c_str()); - if (atoi(tok.c_str()) < 0) - log_error("%s.%s has negative arrival value %s!\n", log_id(m), log_id(port_name), - tok.c_str()); - count++; - } - if (count > 1 && count != GetSize(w)) - log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(m), log_id(port_name), - GetSize(w), log_signal(it->second), count); - } - - it = w->attributes.find("\\abc9_required"); - if (it != w->attributes.end()) { - int count = 0; - if (it->second.flags == 0) { - if (it->second.as_int() < 0) - log_error("%s.%s has negative required value %d!\n", log_id(m), log_id(port_name), - it->second.as_int()); - count++; - } - else - for (const auto &tok : split_tokens(it->second.decode_string())) { - if (tok.find_first_not_of("0123456789") != std::string::npos) - log_error("%s.%s has non-integer required value '%s'!\n", log_id(m), log_id(port_name), - tok.c_str()); - if (atoi(tok.c_str()) < 0) - log_error("%s.%s has negative required value %s!\n", log_id(m), log_id(port_name), - tok.c_str()); - count++; - } - if (count > 1 && count != GetSize(w)) - log_error("%s.%s is %d bits wide but abc9_required = %s has %d value(s)!\n", log_id(m), log_id(port_name), - GetSize(w), log_signal(it->second), count); - } } if (carry_in != IdString() && carry_out == IdString()) @@ -143,9 +93,10 @@ void check(RTLIL::Design *design) void mark_scc(RTLIL::Module *module) { // For every unique SCC found, (arbitrarily) find the first - // cell in the component, and convert all wires driven by - // its output ports into a new PO, and drive its previous - // sinks with a new PI + // cell in the component, and replace its output connections + // with a new wire driven by the old connection but with a + // special (* abc9_scc *) attribute set (which is used by + // write_xaiger to break this wire into PI and POs) pool<RTLIL::Const> ids_seen; for (auto cell : module->cells()) { auto it = cell->attributes.find(ID(abc9_scc_id)); @@ -159,15 +110,13 @@ void mark_scc(RTLIL::Module *module) for (auto &c : cell->connections_) { if (c.second.is_fully_const()) continue; if (cell->output(c.first)) { - SigBit b = c.second.as_bit(); - Wire *w = b.wire; - w->set_bool_attribute(ID::keep); - w->attributes[ID(abc9_scc_id)] = id.as_int(); + Wire *w = module->addWire(NEW_ID, GetSize(c.second)); + w->set_bool_attribute(ID(abc9_scc)); + module->connect(w, c.second); + c.second = w; } } } - - module->fixup_ports(); } void prep_dff(RTLIL::Module *module) @@ -192,20 +141,9 @@ void prep_dff(RTLIL::Module *module) clkdomain_t key(abc9_clock); auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1)); - auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second)); - log_assert(r2.second); - - Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str())); - if (abc9_init_wire == NULL) - log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module)); - log_assert(GetSize(abc9_init_wire) == 1); - SigSpec abc9_init = assign_map(abc9_init_wire); - if (!abc9_init.is_fully_const()) - log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module)); - if (abc9_init == State::S1) - log_error("'%s.init' in module '%s' has value 1'b1 which is not supported by 'abc9 -dff'.\n", cell->name.c_str(), log_id(module)); - r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const())); + auto r2 = cell->attributes.insert(ID(abc9_mergeability));; log_assert(r2.second); + r2.first->second = r.first->second; } RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str())); @@ -280,7 +218,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) if (abc9_flop && !dff) continue; - if ((inst_module && inst_module->attributes.count("\\abc9_box_id")) || abc9_flop) { + if ((inst_module && inst_module->get_bool_attribute("\\abc9_box")) || abc9_flop) { auto r = box_ports.insert(cell->type); if (r.second) { // Make carry in the last PI, and carry out the last PO @@ -327,8 +265,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff) for (auto &it : bit_users) if (bit_drivers.count(it.first)) for (auto driver_cell : bit_drivers.at(it.first)) - for (auto user_cell : it.second) - toposort.edge(driver_cell, user_cell); + for (auto user_cell : it.second) + toposort.edge(driver_cell, user_cell); if (ys_debug(1)) toposort.analyze_loops = true; @@ -354,6 +292,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) holes_module->set_bool_attribute("\\abc9_holes"); dict<IdString, Cell*> cell_cache; + TimingInfo timing; int port_id = 1, box_count = 0; for (auto cell_name : toposort.sorted) { @@ -361,7 +300,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) log_assert(cell); RTLIL::Module* box_module = design->module(cell->type); - if (!box_module || (!box_module->attributes.count("\\abc9_box_id") && !box_module->get_bool_attribute("\\abc9_flop"))) + if (!box_module || (!box_module->get_bool_attribute("\\abc9_box") && !box_module->get_bool_attribute("\\abc9_flop"))) continue; cell->attributes["\\abc9_box_seq"] = box_count++; @@ -440,19 +379,20 @@ void prep_xaiger(RTLIL::Module *module, bool dff) } } -void prep_delays(RTLIL::Design *design) +void prep_delays(RTLIL::Design *design, bool dff_mode) { - std::set<int> delays; + TimingInfo timing; + + // Derive all Yosys blackbox modules that are not combinatorial abc9 boxes + // (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations pool<Module*> flops; std::vector<Cell*> cells; - dict<IdString,dict<IdString,std::vector<int>>> requireds_cache; for (auto module : design->selected_modules()) { if (module->processes.size() > 0) { log("Skipping module %s as it contains processes.\n", log_id(module)); continue; } - cells.clear(); for (auto cell : module->cells()) { if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY))) continue; @@ -462,144 +402,311 @@ void prep_delays(RTLIL::Design *design) continue; if (!inst_module->get_blackbox_attribute()) continue; - if (inst_module->get_bool_attribute(ID(abc9_flop))) { - IdString derived_type = inst_module->derive(design, cell->parameters); - inst_module = design->module(derived_type); - log_assert(inst_module); + if (inst_module->attributes.count(ID(abc9_box))) + continue; + IdString derived_type = inst_module->derive(design, cell->parameters); + inst_module = design->module(derived_type); + log_assert(inst_module); + + if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) { flops.insert(inst_module); - continue; // because all flop required times - // will be captured in the flop box + continue; // do not add $__ABC9_DELAY boxes to flops + // as delays will be captured in the flop box } - if (inst_module->attributes.count(ID(abc9_box_id))) - continue; + + if (!timing.count(derived_type)) + timing.setup_module(inst_module); + cells.emplace_back(cell); } + } - delays.clear(); - for (auto cell : cells) { - RTLIL::Module* inst_module = module->design->module(cell->type); - log_assert(inst_module); - auto &cell_requireds = requireds_cache[cell->type]; - for (auto &conn : cell->connections_) { - auto port_wire = inst_module->wire(conn.first); - if (!port_wire->port_input) + // Insert $__ABC9_DELAY cells on all cells that instantiate blackboxes + // with required times + for (auto cell : cells) { + auto module = cell->module; + RTLIL::Module* inst_module = module->design->module(cell->type); + log_assert(inst_module); + IdString derived_type = inst_module->derive(design, cell->parameters); + inst_module = design->module(derived_type); + log_assert(inst_module); + + auto &t = timing.at(derived_type).required; + for (auto &conn : cell->connections_) { + auto port_wire = inst_module->wire(conn.first); + if (!port_wire->port_input) + continue; + + SigSpec O = module->addWire(NEW_ID, GetSize(conn.second)); + for (int i = 0; i < GetSize(conn.second); i++) { + auto d = t.at(TimingInfo::NameBit(conn.first,i), 0); + if (d == 0) continue; - auto r = cell_requireds.insert(conn.first); - auto &requireds = r.first->second; - if (r.second) { - auto it = port_wire->attributes.find("\\abc9_required"); - if (it == port_wire->attributes.end()) +#ifndef NDEBUG + if (ys_debug(1)) { + static std::set<std::tuple<IdString,IdString,int>> seen; + if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_required = %d\n", + log_id(cell->type), log_id(conn.first), i, d); + } +#endif + auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY)); + box->setPort(ID(I), conn.second[i]); + box->setPort(ID(O), O[i]); + box->setParam(ID(DELAY), d); + conn.second[i] = O[i]; + } + } + } +} + +void prep_lut(RTLIL::Design *design, int maxlut) +{ + TimingInfo timing; + + std::vector<std::tuple<int, IdString, int, std::vector<int>>> table; + for (auto module : design->modules()) { + auto it = module->attributes.find(ID(abc9_lut)); + if (it == module->attributes.end()) + continue; + + auto &t = timing.setup_module(module); + + TimingInfo::NameBit o; + std::vector<int> specify; + for (const auto &i : t.comb) { + auto &d = i.first.second; + if (o == TimingInfo::NameBit()) + o = d; + else if (o != d) + log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module)); + specify.push_back(i.second); + } + + if (maxlut && GetSize(specify) > maxlut) + continue; + // ABC requires non-decreasing LUT input delays + std::sort(specify.begin(), specify.end()); + table.emplace_back(GetSize(specify), module->name, it->second.as_int(), std::move(specify)); + } + // ABC requires ascending size + std::sort(table.begin(), table.end()); + + std::stringstream ss; + const auto &first = table.front(); + // If the first entry does not start from a 1-input LUT, + // (as ABC requires) crop the first entry to do so + for (int i = 1; i < std::get<0>(first); i++) { + ss << "# $__ABC9_LUT" << i << std::endl; + ss << i << " " << std::get<2>(first); + for (int j = 0; j < i; j++) + ss << " " << std::get<3>(first)[j]; + ss << std::endl; + } + for (const auto &i : table) { + ss << "# " << log_id(std::get<1>(i)) << std::endl; + ss << std::get<0>(i) << " " << std::get<2>(i); + for (const auto &j : std::get<3>(i)) + ss << " " << j; + ss << std::endl; + } + design->scratchpad_set_string("abc9_ops.lut_library", ss.str()); +} + +void write_lut(RTLIL::Module *module, const std::string &dst) { + std::ofstream ofs(dst); + log_assert(ofs.is_open()); + ofs << module->design->scratchpad_get_string("abc9_ops.lut_library"); + ofs.close(); +} + +void prep_box(RTLIL::Design *design, bool dff_mode) +{ + TimingInfo timing; + + std::stringstream ss; + int abc9_box_id = 1; + for (auto module : design->modules()) { + auto it = module->attributes.find(ID(abc9_box_id)); + if (it == module->attributes.end()) + continue; + abc9_box_id = std::max(abc9_box_id, it->second.as_int()); + } + + dict<IdString,std::vector<IdString>> box_ports; + for (auto module : design->modules()) { + auto abc9_flop = module->get_bool_attribute(ID(abc9_flop)); + if (abc9_flop) { + auto r = module->attributes.insert(ID(abc9_box_id)); + if (!r.second) + continue; + r.first->second = abc9_box_id++; + + if (dff_mode) { + int num_inputs = 0, num_outputs = 0; + for (auto port_name : module->ports) { + auto wire = module->wire(port_name); + log_assert(GetSize(wire) == 1); + if (wire->port_input) num_inputs++; + if (wire->port_output) num_outputs++; + } + log_assert(num_outputs == 1); + + ss << log_id(module) << " " << r.first->second.as_int(); + ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0"); + ss << " " << num_inputs+1 << " " << num_outputs << std::endl; + + ss << "#"; + bool first = true; + for (auto port_name : module->ports) { + auto wire = module->wire(port_name); + if (!wire->port_input) continue; - if (it->second.flags == 0) { - int delay = it->second.as_int(); - delays.insert(delay); - requireds.emplace_back(delay); - } + if (first) + first = false; else - for (const auto &tok : split_tokens(it->second.decode_string())) { - int delay = atoi(tok.c_str()); - delays.insert(delay); - requireds.push_back(delay); - } + ss << " "; + ss << log_id(wire); } + ss << " abc9_ff.Q" << std::endl; - if (requireds.empty()) - continue; + auto &t = timing.setup_module(module).required; + first = true; + for (auto port_name : module->ports) { + auto wire = module->wire(port_name); + if (!wire->port_input) + continue; + if (first) + first = false; + else + ss << " "; + log_assert(GetSize(wire) == 1); + auto it = t.find(TimingInfo::NameBit(port_name,0)); + if (it == t.end()) + // Assume that no setup time means zero + ss << 0; + else { + ss << it->second; - SigSpec O = module->addWire(NEW_ID, GetSize(conn.second)); - auto it = requireds.begin(); - for (int i = 0; i < GetSize(conn.second); ++i) { #ifndef NDEBUG - if (ys_debug(1)) { - static std::set<std::pair<IdString,IdString>> seen; - if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]); - } + if (ys_debug(1)) { + static std::set<std::pair<IdString,IdString>> seen; + if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module), + log_id(port_name), it->second); + } #endif - auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY)); - box->setPort(ID(I), conn.second[i]); - box->setPort(ID(O), O[i]); - box->setParam(ID(DELAY), *it); - if (requireds.size() > 1) - it++; - conn.second[i] = O[i]; + } + } + // Last input is 'abc9_ff.Q' + ss << " 0" << std::endl << std::endl; + continue; } } + else { + if (!module->attributes.erase(ID(abc9_box))) + continue; - std::stringstream ss; - bool first = true; - for (auto d : delays) { - if (first) - first = false; - else - ss << " "; - ss << d; + auto r = module->attributes.insert(ID(abc9_box_id)); + if (!r.second) + continue; + r.first->second = abc9_box_id++; } - module->attributes[ID(abc9_delays)] = ss.str(); - } - int flops_id = ABC9_FLOPS_BASE_ID; - std::stringstream ss; - for (auto flop_module : flops) { - int num_inputs = 0, num_outputs = 0; - for (auto port_name : flop_module->ports) { - auto wire = flop_module->wire(port_name); - if (wire->port_input) num_inputs++; - if (wire->port_output) num_outputs++; + auto r = box_ports.insert(module->name); + if (r.second) { + // Make carry in the last PI, and carry out the last PO + // since ABC requires it this way + IdString carry_in, carry_out; + for (const auto &port_name : module->ports) { + auto w = module->wire(port_name); + log_assert(w); + if (w->get_bool_attribute("\\abc9_carry")) { + log_assert(w->port_input != w->port_output); + if (w->port_input) + carry_in = port_name; + else if (w->port_output) + carry_out = port_name; + } + else + r.first->second.push_back(port_name); + } + + if (carry_in != IdString()) { + r.first->second.push_back(carry_in); + r.first->second.push_back(carry_out); + } + } + + std::vector<SigBit> inputs; + std::vector<SigBit> outputs; + for (auto port_name : r.first->second) { + auto wire = module->wire(port_name); + if (wire->port_input) + for (int i = 0; i < GetSize(wire); i++) + inputs.emplace_back(wire, i); + if (wire->port_output) + for (int i = 0; i < GetSize(wire); i++) + outputs.emplace_back(wire, i); } - log_assert(num_outputs == 1); - auto r = flop_module->attributes.insert(ID(abc9_box_id)); - if (r.second) - r.first->second = flops_id++; + ss << log_id(module) << " " << module->attributes.at(ID(abc9_box_id)).as_int(); + ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0"); + ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl; - ss << log_id(flop_module) << " " << r.first->second.as_int(); - ss << " 1 " << num_inputs+1 << " " << num_outputs << std::endl; bool first = true; - for (auto port_name : flop_module->ports) { - auto wire = flop_module->wire(port_name); - if (!wire->port_input) - continue; + ss << "#"; + for (const auto &i : inputs) { if (first) first = false; else ss << " "; - ss << wire->attributes.at("\\abc9_required", 0).as_int(); + if (GetSize(i.wire) == 1) + ss << log_id(i.wire); + else + ss << log_id(i.wire) << "[" << i.offset << "]"; } - // Last input is 'abc9_ff.Q' - ss << " 0" << std::endl << std::endl; - } - design->scratchpad_set_string("abc9_ops.box.flops", ss.str()); -} - -void write_box(RTLIL::Module *module, const std::string &src, const std::string &dst) { - std::ofstream ofs(dst); - log_assert(ofs.is_open()); + ss << std::endl; - // Since ABC can only accept one box file, we have to copy - // over the existing box file - if (src != "(null)") { - std::ifstream ifs(src); - ofs << ifs.rdbuf() << std::endl; - ifs.close(); - } + auto &t = timing.setup_module(module).comb; + if (!abc9_flop && t.empty()) + log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module)); - ofs << module->design->scratchpad_get_string("abc9_ops.box.flops"); + for (const auto &o : outputs) { + first = true; + for (const auto &i : inputs) { + if (first) + first = false; + else + ss << " "; + auto jt = t.find(TimingInfo::BitBit(i,o)); + if (jt == t.end()) + ss << "-"; + else + ss << jt->second; + } + ss << " # "; + if (GetSize(o.wire) == 1) + ss << log_id(o.wire); + else + ss << log_id(o.wire) << "[" << o.offset << "]"; + ss << std::endl; - auto it = module->attributes.find(ID(abc9_delays)); - if (it != module->attributes.end()) { - for (const auto &tok : split_tokens(it->second.decode_string())) { - int d = atoi(tok.c_str()); - ofs << "$__ABC9_DELAY@" << d << " " << ABC9_DELAY_BASE_ID + d << " 0 1 1" << std::endl; - ofs << d << std::endl; } - module->attributes.erase(it); + ss << std::endl; } - if (ofs.tellp() == 0) - ofs << "(dummy) 1 0 0 0"; + // ABC expects at least one box + if (ss.tellp() == 0) + ss << "(dummy) 1 0 0 0"; + + design->scratchpad_set_string("abc9_ops.box_library", ss.str()); +} +void write_box(RTLIL::Module *module, const std::string &dst) { + std::ofstream ofs(dst); + log_assert(ofs.is_open()); + ofs << module->design->scratchpad_get_string("abc9_ops.box_library"); ofs.close(); } @@ -763,13 +870,11 @@ void reintegrate(RTLIL::Module *module) continue; } -#ifndef NDEBUG RTLIL::Module* box_module = design->module(existing_cell->type); IdString derived_type = box_module->derive(design, existing_cell->parameters); RTLIL::Module* derived_module = design->module(derived_type); log_assert(derived_module); log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int())); -#endif mapped_cell->type = existing_cell->type; RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type); @@ -861,10 +966,8 @@ void reintegrate(RTLIL::Module *module) RTLIL::Wire *mapped_wire = mapped_mod->wire(port); RTLIL::Wire *wire = module->wire(port); log_assert(wire); - if (wire->attributes.erase(ID(abc9_scc_id))) { - auto r YS_ATTRIBUTE(unused) = wire->attributes.erase(ID::keep); - log_assert(r); - } + wire->attributes.erase(ID(abc9_scc)); + RTLIL::Wire *remap_wire = module->wire(remap_name(port)); RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire)); @@ -993,7 +1096,7 @@ struct Abc9OpsPass : public Pass { log("\n"); log(" -prep_delays\n"); log(" insert `$__ABC9_DELAY' blackbox cells into the design to account for\n"); - log(" certain delays, e.g. (* abc9_required *) values.\n"); + log(" certain required times.\n"); log("\n"); log(" -mark_scc\n"); log(" for an arbitrarily chosen cell in each unique SCC of each selected module\n"); @@ -1008,16 +1111,26 @@ struct Abc9OpsPass : public Pass { log(" whiteboxes.\n"); log("\n"); log(" -dff\n"); - log(" consider flop cells (those instantiating modules marked with (* abc9_flop *)\n"); - log(" during -prep_xaiger.\n"); + log(" consider flop cells (those instantiating modules marked with (* abc9_flop *))\n"); + log(" during -prep_{delays,xaiger,box}.\n"); log("\n"); log(" -prep_dff\n"); log(" compute the clock domain and initial value of each flop in the design.\n"); log(" process the '$holes' module to support clock-enable functionality.\n"); log("\n"); - log(" -write_box (<src>|(null)) <dst>\n"); - log(" copy the existing box file from <src> (skip if '(null)') and append any\n"); - log(" new box definitions.\n"); + log(" -prep_lut <maxlut>\n"); + log(" pre-compute the lut library by analysing all modules marked with\n"); + log(" (* abc9_lut=<area> *).\n"); + log("\n"); + log(" -write_lut <dst>\n"); + log(" write the pre-computed lut library to <dst>.\n"); + log("\n"); + log(" -prep_box\n"); + log(" pre-compute the box library by analysing all modules marked with\n"); + log(" (* abc9_box *).\n"); + log("\n"); + log(" -write_box <dst>\n"); + log(" write the pre-computed box library to <dst>.\n"); log("\n"); log(" -reintegrate\n"); log(" for each selected module, re-intergrate the module '<module-name>$abc9'\n"); @@ -1034,9 +1147,13 @@ struct Abc9OpsPass : public Pass { bool mark_scc_mode = false; bool prep_dff_mode = false; bool prep_xaiger_mode = false; + bool prep_lut_mode = false; + bool prep_box_mode = false; bool reintegrate_mode = false; bool dff_mode = false; - std::string write_box_src, write_box_dst; + std::string write_lut_dst; + int maxlut = 0; + std::string write_box_dst; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -1061,10 +1178,25 @@ struct Abc9OpsPass : public Pass { prep_delays_mode = true; continue; } - if (arg == "-write_box" && argidx+2 < args.size()) { - write_box_src = args[++argidx]; + if (arg == "-prep_lut" && argidx+1 < args.size()) { + prep_lut_mode = true; + maxlut = atoi(args[++argidx].c_str()); + continue; + } + if (arg == "-maxlut" && argidx+1 < args.size()) { + continue; + } + if (arg == "-write_lut" && argidx+1 < args.size()) { + write_lut_dst = args[++argidx]; + rewrite_filename(write_lut_dst); + continue; + } + if (arg == "-prep_box") { + prep_box_mode = true; + continue; + } + if (arg == "-write_box" && argidx+1 < args.size()) { write_box_dst = args[++argidx]; - rewrite_filename(write_box_src); rewrite_filename(write_box_dst); continue; } @@ -1080,16 +1212,20 @@ struct Abc9OpsPass : public Pass { } extra_args(args, argidx, design); - if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || !write_box_src.empty() || reintegrate_mode)) - log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff}, -write_box, -reintegrate must be specified.\n"); + if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || prep_box_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode)) + log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n"); - if (dff_mode && !prep_xaiger_mode) - log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n"); + if (dff_mode && !prep_delays_mode && !prep_xaiger_mode && !prep_box_mode) + log_cmd_error("'-dff' option is only relevant for -prep_{delay,xaiger,box}.\n"); if (check_mode) check(design); if (prep_delays_mode) - prep_delays(design); + prep_delays(design, dff_mode); + if (prep_lut_mode) + prep_lut(design, maxlut); + if (prep_box_mode) + prep_box(design, dff_mode); for (auto mod : design->selected_modules()) { if (mod->get_bool_attribute("\\abc9_holes")) @@ -1103,8 +1239,10 @@ struct Abc9OpsPass : public Pass { if (!design->selected_whole_module(mod)) log_error("Can't handle partially selected module %s!\n", log_id(mod)); - if (!write_box_src.empty()) - write_box(mod, write_box_src, write_box_dst); + if (!write_lut_dst.empty()) + write_lut(mod, write_lut_dst); + if (!write_box_dst.empty()) + write_box(mod, write_box_dst); if (mark_scc_mode) mark_scc(mod); if (prep_dff_mode) diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index b976b401b..35d43b106 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -121,8 +121,7 @@ struct DeminoutPass : public Pass { goto tribuf_bit; } else { tribuf_bit: - if (bits_used.count(bit)) - new_input = true; + new_input = true; } } diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index 17a99493d..639ae145b 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -90,22 +90,35 @@ bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index) struct CounterExtraction { int width; //counter width + bool count_is_up; //count up (else down) RTLIL::Wire* rwire; //the register output bool has_reset; //true if we have a reset bool has_ce; //true if we have a clock enable + bool ce_inverted; //true if clock enable is active low RTLIL::SigSpec rst; //reset pin bool rst_inverted; //true if reset is active low bool rst_to_max; //true if we reset to max instead of 0 int count_value; //value we count from RTLIL::SigSpec ce; //clock signal RTLIL::SigSpec clk; //clock enable, if any - RTLIL::SigSpec outsig; //counter output signal + RTLIL::SigSpec outsig; //counter overflow output signal + RTLIL::SigSpec poutsig; //counter parallel output signal + bool has_pout; //whether parallel output is used RTLIL::Cell* count_mux; //counter mux RTLIL::Cell* count_reg; //counter register - RTLIL::Cell* underflow_inv; //inverter reduction for output-underflow detect + RTLIL::Cell* overflow_cell; //cell for counter overflow (either inverter reduction or $eq) pool<ModIndex::PortInfo> pouts; //Ports that take a parallel output from us }; +struct CounterExtractionSettings +{ + pool<RTLIL::IdString>& parallel_cells; + int maxwidth; + int minwidth; + bool allow_arst; + int allowed_dirs; //0 = down, 1 = up, 2 = both +}; + //attempt to extract a counter centered on the given adder cell //For now we only support DOWN counters. //TODO: up/down support @@ -113,49 +126,132 @@ int counter_tryextract( ModIndex& index, Cell *cell, CounterExtraction& extract, - pool<RTLIL::IdString>& parallel_cells, - int maxwidth) + CounterExtractionSettings settings) { SigMap& sigmap = index.sigmap; - //A counter with less than 2 bits makes no sense - //TODO: configurable min threshold - int a_width = cell->getParam(ID(A_WIDTH)).as_int(); - extract.width = a_width; - if( (a_width < 2) || (a_width > maxwidth) ) - return 1; - - //Second input must be a single bit - int b_width = cell->getParam(ID(B_WIDTH)).as_int(); - if(b_width != 1) - return 2; - //Both inputs must be unsigned, so don't extract anything with a signed input bool a_sign = cell->getParam(ID(A_SIGNED)).as_bool(); bool b_sign = cell->getParam(ID(B_SIGNED)).as_bool(); if(a_sign || b_sign) return 3; - //To be a counter, one input of the ALU must be a constant 1 - //TODO: can A or B be swapped in synthesized RTL or is B always the 1? - const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B)); - if(!b_port.is_fully_const() || (b_port.as_int() != 1) ) - return 4; - - //BI and CI must be constant 1 as well - const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID(BI))); - if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) ) - return 5; - const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID(CI))); - if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) ) - return 6; - //CO and X must be unconnected (exactly one connection to each port) if(!is_unconnected(sigmap(cell->getPort(ID(CO))), index)) return 7; if(!is_unconnected(sigmap(cell->getPort(ID(X))), index)) return 8; + //true if $alu is performing A - B, else A + B + bool alu_is_subtract; + + //BI and CI must be both constant 0 or both constant 1 as well + const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID(BI))); + const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID(CI))); + if(bi_port.is_fully_const() && bi_port.as_int() == 1 && + ci_port.is_fully_const() && ci_port.as_int() == 1) + { + alu_is_subtract = true; + } + else if(bi_port.is_fully_const() && bi_port.as_int() == 0 && + ci_port.is_fully_const() && ci_port.as_int() == 0) + { + alu_is_subtract = false; + } + else + { + return 5; + } + + //false -> port B connects to value + //true -> port A connects to value + bool alu_port_use_a = false; + + if(alu_is_subtract) + { + const int a_width = cell->getParam(ID(A_WIDTH)).as_int(); + const int b_width = cell->getParam(ID(B_WIDTH)).as_int(); + const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B)); + + // down, cnt <= cnt - 1 + if (b_width == 1 && b_port.is_fully_const() && b_port.as_int() == 1) + { + // OK + alu_port_use_a = true; + extract.count_is_up = false; + } + + // up, cnt <= cnt - -1 + else if (b_width == a_width && b_port.is_fully_const() && b_port.is_fully_ones()) + { + // OK + alu_port_use_a = true; + extract.count_is_up = true; + } + + // ??? + else + { + return 2; + } + } + else + { + const int a_width = cell->getParam(ID(A_WIDTH)).as_int(); + const int b_width = cell->getParam(ID(B_WIDTH)).as_int(); + const RTLIL::SigSpec a_port = sigmap(cell->getPort(ID::A)); + const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B)); + + // down, cnt <= cnt + -1 + if (b_width == a_width && b_port.is_fully_const() && b_port.is_fully_ones()) + { + // OK + alu_port_use_a = true; + extract.count_is_up = false; + } + else if (a_width == b_width && a_port.is_fully_const() && a_port.is_fully_ones()) + { + // OK + alu_port_use_a = false; + extract.count_is_up = false; + } + + // up, cnt <= cnt + 1 + else if (b_width == 1 && b_port.is_fully_const() && b_port.as_int() == 1) + { + // OK + alu_port_use_a = true; + extract.count_is_up = true; + } + else if (a_width == 1 && a_port.is_fully_const() && a_port.as_int() == 1) + { + // OK + alu_port_use_a = false; + extract.count_is_up = true; + } + + // ??? + else + { + return 2; + } + } + + if (extract.count_is_up && settings.allowed_dirs == 0) + return 26; + if (!extract.count_is_up && settings.allowed_dirs == 1) + return 26; + + //Check if counter is an appropriate size + int count_width; + if (alu_port_use_a) + count_width = cell->getParam(ID(A_WIDTH)).as_int(); + else + count_width = cell->getParam(ID(B_WIDTH)).as_int(); + extract.width = count_width; + if( (count_width < settings.minwidth) || (count_width > settings.maxwidth) ) + return 1; + //Y must have exactly one connection, and it has to be a $mux cell. //We must have a direct bus connection from our Y to their A. const RTLIL::SigSpec aluy = sigmap(cell->getPort(ID::Y)); @@ -169,30 +265,43 @@ int counter_tryextract( if(!is_full_bus(aluy, index, cell, ID::Y, count_mux, ID::A)) return 11; - //B connection of the mux is our underflow value - const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B)); - if(!underflow.is_fully_const()) - return 12; - extract.count_value = underflow.as_int(); + if (extract.count_is_up) + { + //B connection of the mux must be 0 + const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B)); + if(!(underflow.is_fully_const() && underflow.is_fully_zero())) + return 12; + } + else + { + //B connection of the mux is our underflow value + const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B)); + if(!underflow.is_fully_const()) + return 12; + extract.count_value = underflow.as_int(); + } - //S connection of the mux must come from an inverter (need not be the only load) + //S connection of the mux must come from an inverter if down, eq if up + //(need not be the only load) const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(ID(S))); extract.outsig = muxsel; pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux); - Cell* underflow_inv = NULL; + Cell* overflow_cell = NULL; for(auto c : muxsel_conns) { - if(c->type != ID($logic_not)) + if(extract.count_is_up && c->type != ID($eq)) + continue; + if(!extract.count_is_up && c->type != ID($logic_not)) continue; if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID(S), true)) continue; - underflow_inv = c; + overflow_cell = c; break; } - if(underflow_inv == NULL) + if(overflow_cell == NULL) return 13; - extract.underflow_inv = underflow_inv; + extract.overflow_cell = overflow_cell; //Y connection of the mux must have exactly one load, the counter's internal register, if there's no clock enable //If we have a clock enable, Y drives the B input of a mux. A of that mux must come from our register @@ -215,14 +324,24 @@ int counter_tryextract( return 24; count_reg = *cey_loads.begin(); - //Mux should have A driven by count Q, and B by muxy - //TODO: if A and B are swapped, CE polarity is inverted - if(sigmap(cemux->getPort(ID::B)) != muxy) - return 24; - if(sigmap(cemux->getPort(ID::A)) != sigmap(count_reg->getPort(ID(Q)))) - return 24; if(sigmap(cemux->getPort(ID::Y)) != sigmap(count_reg->getPort(ID(D)))) return 24; + //Mux should have A driven by count Q, and B by muxy + //if A and B are swapped, CE polarity is inverted + if(sigmap(cemux->getPort(ID::B)) == muxy && + sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID(Q)))) + { + extract.ce_inverted = false; + } + else if(sigmap(cemux->getPort(ID::A)) == muxy && + sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID(Q)))) + { + extract.ce_inverted = true; + } + else + { + return 24; + } //Select of the mux is our clock enable extract.has_ce = true; @@ -236,6 +355,9 @@ int counter_tryextract( extract.has_reset = false; else if(count_reg->type == ID($adff)) { + if (!settings.allow_arst) + return 25; + extract.has_reset = true; //Check polarity of reset - we may have to add an inverter later on! @@ -260,7 +382,9 @@ int counter_tryextract( //Sanity check that we use the ALU output properly if(extract.has_ce) { - if(!is_full_bus(muxy, index, count_mux, ID::Y, cemux, ID::B)) + if(!extract.ce_inverted && !is_full_bus(muxy, index, count_mux, ID::Y, cemux, ID::B)) + return 16; + if(extract.ce_inverted && !is_full_bus(muxy, index, count_mux, ID::Y, cemux, ID::A)) return 16; if(!is_full_bus(cey, index, cemux, ID::Y, count_reg, ID(D))) return 16; @@ -274,6 +398,8 @@ int counter_tryextract( //(unless we have a parallel output!) //If we have a clock enable, 3 is OK const RTLIL::SigSpec qport = count_reg->getPort(ID(Q)); + extract.poutsig = qport; + extract.has_pout = false; const RTLIL::SigSpec cnout = sigmap(qport); pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg); unsigned int max_loads = 2; @@ -283,7 +409,7 @@ int counter_tryextract( { for(auto c : cnout_loads) { - if(c == underflow_inv) + if(c == overflow_cell) continue; if(c == cell) continue; @@ -291,15 +417,16 @@ int counter_tryextract( continue; //If we specified a limited set of cells for parallel output, check that we only drive them - if(!parallel_cells.empty()) + if(!settings.parallel_cells.empty()) { //Make sure we're in the whitelist - if( parallel_cells.find(c->type) == parallel_cells.end()) + if( settings.parallel_cells.find(c->type) == settings.parallel_cells.end()) return 17; } //Figure out what port(s) are driven by it //TODO: this can probably be done more efficiently w/o multiple iterations over our whole net? + //TODO: For what purpose do we actually need extract.pouts? for(auto b : qport) { pool<ModIndex::PortInfo> ports = index.query_ports(b); @@ -308,25 +435,75 @@ int counter_tryextract( if(x.cell != c) continue; extract.pouts.insert(ModIndex::PortInfo(c, x.port, 0)); + extract.has_pout = true; } } } } - if(!is_full_bus(cnout, index, count_reg, ID(Q), underflow_inv, ID::A, true)) - return 18; - if(!is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::A, true)) + for (auto b : qport) + { + if(index.query_is_output(b)) + { + // Parallel out goes out of module + extract.has_pout = true; + } + } + if(!extract.count_is_up) + { + if(!is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::A, true)) + return 18; + } + else + { + if(is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::A, true)) + { + // B must be the overflow value + const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::B)); + if(!overflow.is_fully_const()) + return 12; + extract.count_value = overflow.as_int(); + } + else if(is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::B, true)) + { + // A must be the overflow value + const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::A)); + if(!overflow.is_fully_const()) + return 12; + extract.count_value = overflow.as_int(); + } + else + { + return 18; + } + } + if(alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::A, true)) + return 19; + if(!alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::B, true)) return 19; //Look up the clock from the register extract.clk = sigmap(count_reg->getPort(ID(CLK))); - //Register output net must have an INIT attribute equal to the count value - extract.rwire = cnout.as_wire(); - if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end()) - return 20; - int rinit = extract.rwire->attributes[ID(init)].as_int(); - if(rinit != extract.count_value) - return 21; + if(!extract.count_is_up) + { + //Register output net must have an INIT attribute equal to the count value + extract.rwire = cnout.as_wire(); + if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end()) + return 20; + int rinit = extract.rwire->attributes[ID(init)].as_int(); + if(rinit != extract.count_value) + return 21; + } + else + { + //Register output net must not have an INIT attribute or it must be zero + extract.rwire = cnout.as_wire(); + if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end()) + return 0; + int rinit = extract.rwire->attributes[ID(init)].as_int(); + if(rinit != 0) + return 21; + } return 0; } @@ -337,8 +514,7 @@ void counter_worker( unsigned int& total_counters, pool<Cell*>& cells_to_remove, pool<pair<Cell*, string>>& cells_to_rename, - pool<RTLIL::IdString>& parallel_cells, - int maxwidth) + CounterExtractionSettings settings) { SigMap& sigmap = index.sigmap; @@ -350,20 +526,24 @@ void counter_worker( //If it's not a wire, don't even try auto port = sigmap(cell->getPort(ID::A)); if(!port.is_wire()) - return; - RTLIL::Wire* a_wire = port.as_wire(); + { + port = sigmap(cell->getPort(ID::B)); + if(!port.is_wire()) + return; + } + RTLIL::Wire* port_wire = port.as_wire(); bool force_extract = false; bool never_extract = false; - string count_reg_src = a_wire->attributes[ID(src)].decode_string().c_str(); - if(a_wire->attributes.find(ID(COUNT_EXTRACT)) != a_wire->attributes.end()) + string count_reg_src = port_wire->attributes[ID(src)].decode_string().c_str(); + if(port_wire->attributes.find(ID(COUNT_EXTRACT)) != port_wire->attributes.end()) { - pool<string> sa = a_wire->get_strpool_attribute(ID(COUNT_EXTRACT)); + pool<string> sa = port_wire->get_strpool_attribute(ID(COUNT_EXTRACT)); string extract_value; if(sa.size() >= 1) { extract_value = *sa.begin(); log(" Signal %s declared at %s has COUNT_EXTRACT = %s\n", - log_id(a_wire), + log_id(port_wire), count_reg_src.c_str(), extract_value.c_str()); @@ -385,21 +565,21 @@ void counter_worker( //Attempt to extract a counter CounterExtraction extract; - int reason = counter_tryextract(index, cell, extract, parallel_cells, maxwidth); + int reason = counter_tryextract(index, cell, extract, settings); //Nonzero code - we could not find a matchable counter. //Do nothing, unless extraction was forced in which case give an error if(reason != 0) { - static const char* reasons[25]= + static const char* reasons[]= { "no problem", //0 "counter is too large/small", //1 "counter does not count by one", //2 "counter uses signed math", //3 - "counter does not count by one", //4 - "ALU is not a subtractor", //5 - "ALU is not a subtractor", //6 + "RESERVED, not implemented", //4 + "ALU is not an adder/subtractor", //5 + "RESERVED, not implemented", //6 "ALU ports used outside counter", //7 "ALU ports used outside counter", //8 "ALU output used outside counter", //9 @@ -417,14 +597,16 @@ void counter_worker( "Underflow value is not equal to init value", //21 "RESERVED, not implemented", //22, kept for compatibility but not used anymore "Reset is not to zero or COUNT_TO", //23 - "Clock enable configuration is unsupported" //24 + "Clock enable configuration is unsupported", //24 + "Async reset used but not permitted", //25 + "Count direction is not allowed" //26 }; if(force_extract) { log_error( "Counter extraction is set to FORCE on register %s, but a counter could not be inferred (%s)\n", - log_id(a_wire), + log_id(port_wire), reasons[reason]); } return; @@ -483,36 +665,53 @@ void counter_worker( if(extract.has_ce) { cell->setParam(ID(HAS_CE), RTLIL::Const(1)); - cell->setPort(ID(CE), extract.ce); + if(extract.ce_inverted) + { + auto realce = cell->module->addWire(NEW_ID); + cell->module->addNot(NEW_ID, extract.ce, RTLIL::SigSpec(realce)); + cell->setPort(ID(CE), realce); + } + else + cell->setPort(ID(CE), extract.ce); } else + { cell->setParam(ID(HAS_CE), RTLIL::Const(0)); + cell->setPort(ID(CE), RTLIL::Const(1)); + } + + if(extract.count_is_up) + { + cell->setParam(ID(DIRECTION), RTLIL::Const("UP")); + //XXX: What is this supposed to do? + cell->setPort(ID(UP), RTLIL::Const(1)); + } + else + { + cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN")); + cell->setPort(ID(UP), RTLIL::Const(0)); + } - //Hook up hard-wired ports (for now up/down are not supported), default to no parallel output + //Hook up hard-wired ports, default to no parallel output cell->setParam(ID(HAS_POUT), RTLIL::Const(0)); cell->setParam(ID(RESET_TO_MAX), RTLIL::Const(0)); - cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN")); - cell->setPort(ID(CE), RTLIL::Const(1)); - cell->setPort(ID(UP), RTLIL::Const(0)); //Hook up any parallel outputs for(auto load : extract.pouts) { log(" Counter has parallel output to cell %s port %s\n", log_id(load.cell->name), log_id(load.port)); - - //Find the wire hooked to the old port - auto sig = load.cell->getPort(load.port); - + } + if(extract.has_pout) + { //Connect it to our parallel output - //(this is OK to do more than once b/c they all go to the same place) - cell->setPort(ID(POUT), sig); + cell->setPort(ID(POUT), extract.poutsig); cell->setParam(ID(HAS_POUT), RTLIL::Const(1)); } //Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires) cells_to_remove.insert(extract.count_mux); cells_to_remove.insert(extract.count_reg); - cells_to_remove.insert(extract.underflow_inv); + cells_to_remove.insert(extract.overflow_cell); //Log it total_counters ++; @@ -527,17 +726,19 @@ void counter_worker( //TODO: support other kind of reset reset_type += " async resettable"; } - log(" Found %d-bit (%s) down counter %s (counting from %d) for register %s, declared at %s\n", + log(" Found %d-bit (%s) %s counter %s (counting %s %d) for register %s, declared at %s\n", extract.width, reset_type.c_str(), + extract.count_is_up ? "up" : "down", countname.c_str(), + extract.count_is_up ? "to" : "from", extract.count_value, log_id(extract.rwire->name), count_reg_src.c_str()); //Optimize the counter //If we have no parallel output, and we have redundant bits, shrink us - if(extract.pouts.empty()) + if(!extract.has_pout) { //TODO: Need to update this when we add support for counters with nonzero reset values //to make sure the reset value fits in our bit space too @@ -570,7 +771,16 @@ struct ExtractCounterPass : public Pass { log("to the actual target cells.\n"); log("\n"); log(" -maxwidth N\n"); - log(" Only extract counters up to N bits wide\n"); + log(" Only extract counters up to N bits wide (default 64)\n"); + log("\n"); + log(" -minwidth N\n"); + log(" Only extract counters at least N bits wide (default 2)\n"); + log("\n"); + log(" -allow_arst yes|no\n"); + log(" Allow counters to have async reset (default yes)\n"); + log("\n"); + log(" -dir up|down|both\n"); + log(" Look for up-counters, down-counters, or both (default down)\n"); log("\n"); log(" -pout X,Y,...\n"); log(" Only allow parallel output from the counter to the listed cell types\n"); @@ -582,9 +792,17 @@ struct ExtractCounterPass : public Pass { { log_header(design, "Executing EXTRACT_COUNTER pass (find counters in netlist).\n"); - int maxwidth = 64; + pool<RTLIL::IdString> _parallel_cells; + CounterExtractionSettings settings + { + .parallel_cells = _parallel_cells, + .maxwidth = 64, + .minwidth = 2, + .allow_arst = true, + .allowed_dirs = 0, + }; + size_t argidx; - pool<RTLIL::IdString> parallel_cells; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-pout") @@ -601,24 +819,63 @@ struct ExtractCounterPass : public Pass { { if(pouts[i] == ',') { - parallel_cells.insert(RTLIL::escape_id(tmp)); + settings.parallel_cells.insert(RTLIL::escape_id(tmp)); tmp = ""; } else tmp += pouts[i]; } - parallel_cells.insert(RTLIL::escape_id(tmp)); + settings.parallel_cells.insert(RTLIL::escape_id(tmp)); continue; } if (args[argidx] == "-maxwidth" && argidx+1 < args.size()) { - maxwidth = atoi(args[++argidx].c_str()); + settings.maxwidth = atoi(args[++argidx].c_str()); + continue; + } + + if (args[argidx] == "-minwidth" && argidx+1 < args.size()) + { + settings.minwidth = atoi(args[++argidx].c_str()); + continue; + } + + if (args[argidx] == "-allow_arst" && argidx+1 < args.size()) + { + auto arg = args[++argidx]; + if (arg == "yes") + settings.allow_arst = true; + else if (arg == "no") + settings.allow_arst = false; + else + log_error("Invalid -allow_arst value \"%s\"\n", arg.c_str()); + continue; + } + + if (args[argidx] == "-dir" && argidx+1 < args.size()) + { + auto arg = args[++argidx]; + if (arg == "up") + settings.allowed_dirs = 1; + else if (arg == "down") + settings.allowed_dirs = 0; + else if (arg == "both") + settings.allowed_dirs = 2; + else + log_error("Invalid -dir value \"%s\"\n", arg.c_str()); continue; } } extra_args(args, argidx, design); + if (settings.minwidth < 2) + { + //A counter with less than 2 bits makes no sense + log_warning("Minimum counter width is 2 bits wide\n"); + settings.minwidth = 2; + } + //Extract all of the counters we could find unsigned int total_counters = 0; for (auto module : design->selected_modules()) @@ -628,7 +885,7 @@ struct ExtractCounterPass : public Pass { ModIndex index(module); for (auto cell : module->selected_cells()) - counter_worker(index, cell, total_counters, cells_to_remove, cells_to_rename, parallel_cells, maxwidth); + counter_worker(index, cell, total_counters, cells_to_remove, cells_to_rename, settings); for(auto cell : cells_to_remove) { diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 531ac2b99..8b1862237 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -83,6 +83,20 @@ struct IopadmapPass : public Pass { log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n"); log("\n"); } + + void module_queue(Design *design, Module *module, std::vector<Module *> &modules_sorted, pool<Module *> &modules_processed) { + if (modules_processed.count(module)) + return; + for (auto cell : module->cells()) { + Module *submodule = design->module(cell->type); + if (!submodule) + continue; + module_queue(design, submodule, modules_sorted, modules_processed); + } + modules_sorted.push_back(module); + modules_processed.insert(module); + } + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n"); @@ -172,22 +186,49 @@ struct IopadmapPass : public Pass { if (!tinoutpad_portname_pad.empty()) ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname_pad))); - for (auto module : design->modules()) - if (module->get_blackbox_attribute()) - for (auto wire : module->wires()) - if (wire->get_bool_attribute("\\iopad_external_pin")) - ignore.insert(make_pair(module->name, wire->name)); + // Recursively collect list of (module, port, bit) triples that already have buffers. + + pool<pair<IdString, pair<IdString, int>>> buf_ports; + // Process submodules before module using them. + std::vector<Module *> modules_sorted; + pool<Module *> modules_processed; for (auto module : design->selected_modules()) + module_queue(design, module, modules_sorted, modules_processed); + + for (auto module : modules_sorted) { - pool<SigBit> skip_wire_bits; - dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits; + pool<SigBit> buf_bits; + SigMap sigmap(module); + // Collect explicitly-marked already-buffered SigBits. + for (auto wire : module->wires()) + if (wire->get_bool_attribute("\\iopad_external_pin") || ignore.count(make_pair(module->name, wire->name))) + for (int i = 0; i < GetSize(wire); i++) + buf_bits.insert(sigmap(SigBit(wire, i))); + + // Collect SigBits connected to already-buffered ports. for (auto cell : module->cells()) for (auto port : cell->connections()) - if (ignore.count(make_pair(cell->type, port.first))) - for (auto bit : port.second) - skip_wire_bits.insert(bit); + for (int i = 0; i < port.second.size(); i++) + if (buf_ports.count(make_pair(cell->type, make_pair(port.first, i)))) + buf_bits.insert(sigmap(port.second[i])); + + // Now fill buf_ports. + for (auto wire : module->wires()) + if (wire->port_input || wire->port_output) + for (int i = 0; i < GetSize(wire); i++) + if (buf_bits.count(sigmap(SigBit(wire, i)))) { + buf_ports.insert(make_pair(module->name, make_pair(wire->name, i))); + log("Marking already mapped port: %s.%s[%d].\n", log_id(module), log_id(wire), i); + } + } + + // Now do the actual buffer insertion. + + for (auto module : design->selected_modules()) + { + dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits; if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty()) { @@ -234,7 +275,7 @@ struct IopadmapPass : public Pass { SigBit wire_bit(wire, i); Cell *tbuf_cell = nullptr; - if (skip_wire_bits.count(wire_bit)) + if (buf_ports.count(make_pair(module->name, make_pair(wire->name, i)))) continue; if (tbuf_bits.count(wire_bit)) @@ -267,7 +308,9 @@ struct IopadmapPass : public Pass { { log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str()); - Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(tinoutpad_celltype)); + Cell *cell = module->addCell( + module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)), + RTLIL::escape_id(tinoutpad_celltype)); cell->setPort(RTLIL::escape_id(tinoutpad_portname_oe), en_sig); cell->attributes[ID::keep] = RTLIL::Const(1); @@ -282,13 +325,14 @@ struct IopadmapPass : public Pass { cell->setPort(RTLIL::escape_id(tinoutpad_portname_o), wire_bit); cell->setPort(RTLIL::escape_id(tinoutpad_portname_i), data_sig); } - skip_wire_bits.insert(wire_bit); if (!tinoutpad_portname_pad.empty()) rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(tinoutpad_portname_pad)); } else { log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str()); - Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(toutpad_celltype)); + Cell *cell = module->addCell( + module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)), + RTLIL::escape_id(toutpad_celltype)); cell->setPort(RTLIL::escape_id(toutpad_portname_oe), en_sig); cell->setPort(RTLIL::escape_id(toutpad_portname_i), data_sig); @@ -298,10 +342,10 @@ struct IopadmapPass : public Pass { module->remove(tbuf_cell); module->connect(wire_bit, data_sig); } - skip_wire_bits.insert(wire_bit); if (!toutpad_portname_pad.empty()) rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(toutpad_portname_pad)); } + buf_ports.insert(make_pair(module->name, make_pair(wire->name, i))); } } } @@ -315,7 +359,7 @@ struct IopadmapPass : public Pass { pool<int> skip_bit_indices; for (int i = 0; i < GetSize(wire); i++) - if (skip_wire_bits.count(SigBit(wire, i))) + if (buf_ports.count(make_pair(module->name, make_pair(wire->name, i)))) skip_bit_indices.insert(i); if (GetSize(wire) == GetSize(skip_bit_indices)) @@ -366,7 +410,9 @@ struct IopadmapPass : public Pass { SigBit wire_bit(wire, i); - RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); + RTLIL::Cell *cell = module->addCell( + module->uniquify(stringf("$iopadmap$%s.%s", log_id(module->name), log_id(wire->name))), + RTLIL::escape_id(celltype)); cell->setPort(RTLIL::escape_id(portname_int), wire_bit); if (!portname_pad.empty()) @@ -380,12 +426,16 @@ struct IopadmapPass : public Pass { } else { - RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); + RTLIL::Cell *cell = module->addCell( + module->uniquify(stringf("$iopadmap$%s.%s", log_id(module->name), log_id(wire->name))), + RTLIL::escape_id(celltype)); cell->setPort(RTLIL::escape_id(portname_int), RTLIL::SigSpec(wire)); if (!portname_pad.empty()) { RTLIL::Wire *new_wire = NULL; - new_wire = module->addWire(NEW_ID, wire); + new_wire = module->addWire( + module->uniquify(stringf("$iopadmap$%s", log_id(wire))), + wire); module->swap_names(new_wire, wire); wire->attributes.clear(); cell->setPort(RTLIL::escape_id(portname_pad), RTLIL::SigSpec(new_wire)); @@ -406,7 +456,9 @@ struct IopadmapPass : public Pass { for (auto &it : rewrite_bits) { RTLIL::Wire *wire = it.first; - RTLIL::Wire *new_wire = module->addWire(NEW_ID, wire); + RTLIL::Wire *new_wire = module->addWire( + module->uniquify(stringf("$iopadmap$%s", log_id(wire))), + wire); module->swap_names(new_wire, wire); wire->attributes.clear(); for (int i = 0; i < wire->width; i++) @@ -423,6 +475,15 @@ struct IopadmapPass : public Pass { } } + if (wire->port_output) { + auto jt = new_wire->attributes.find(ID(init)); + // For output ports, move \init attributes from old wire to new wire + if (jt != new_wire->attributes.end()) { + wire->attributes[ID(init)] = std::move(jt->second); + new_wire->attributes.erase(jt); + } + } + wire->port_id = 0; wire->port_input = false; wire->port_output = false; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 0c57733d4..10001baaa 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -177,10 +177,10 @@ struct TechmapWorker std::string orig_cell_name; pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src)); + orig_cell_name = cell->name.str(); if (!flatten_mode) { for (auto &it : tpl->cells_) if (it.first == ID(_TECHMAP_REPLACE_)) { - orig_cell_name = cell->name.str(); module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); break; } |