aboutsummaryrefslogtreecommitdiffstats
path: root/passes
diff options
context:
space:
mode:
Diffstat (limited to 'passes')
-rw-r--r--passes/cmds/design.cc67
-rw-r--r--passes/cmds/trace.cc2
-rw-r--r--passes/hierarchy/hierarchy.cc132
-rw-r--r--passes/memory/memory_share.cc32
-rw-r--r--passes/opt/opt_clean.cc8
-rw-r--r--passes/opt/opt_expr.cc124
-rw-r--r--passes/opt/opt_merge.cc234
-rw-r--r--passes/opt/opt_reduce.cc8
-rw-r--r--passes/opt/pmux2shiftx.cc4
-rw-r--r--passes/opt/share.cc62
-rw-r--r--passes/opt/wreduce.cc2
-rw-r--r--passes/proc/proc_prune.cc2
-rw-r--r--passes/sat/clk2fflogic.cc16
-rw-r--r--passes/sat/eval.cc90
-rw-r--r--passes/sat/expose.cc151
-rw-r--r--passes/sat/freduce.cc28
-rw-r--r--passes/techmap/extract_reduce.cc2
-rw-r--r--passes/techmap/flowmap.cc2
-rw-r--r--passes/techmap/techmap.cc4
19 files changed, 503 insertions, 467 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 172addcc1..7ea0be9ee 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -18,6 +18,7 @@
*/
#include "kernel/yosys.h"
+#include "frontends/verilog/preproc.h"
#include "frontends/ast/ast.h"
YOSYS_NAMESPACE_BEGIN
@@ -194,13 +195,13 @@ struct DesignPass : public Pass {
argidx = args.size();
}
- for (auto &it : copy_from_design->modules_) {
- if (sel.selected_whole_module(it.first)) {
- copy_src_modules.push_back(it.second);
+ for (auto mod : copy_from_design->modules()) {
+ if (sel.selected_whole_module(mod->name)) {
+ copy_src_modules.push_back(mod);
continue;
}
- if (sel.selected_module(it.first))
- log_cmd_error("Module %s is only partly selected.\n", RTLIL::id2cstr(it.first));
+ if (sel.selected_module(mod->name))
+ log_cmd_error("Module %s is only partly selected.\n", log_id(mod->name));
}
if (import_mode) {
@@ -230,8 +231,8 @@ struct DesignPass : public Pass {
pool<Module*> queue;
dict<IdString, IdString> done;
- if (copy_to_design->modules_.count(prefix))
- delete copy_to_design->modules_.at(prefix);
+ if (copy_to_design->module(prefix) != nullptr)
+ copy_to_design->remove(copy_to_design->module(prefix));
if (GetSize(copy_src_modules) != 1)
log_cmd_error("No top module found in source design.\n");
@@ -240,12 +241,13 @@ struct DesignPass : public Pass {
{
log("Importing %s as %s.\n", log_id(mod), log_id(prefix));
- copy_to_design->modules_[prefix] = mod->clone();
- copy_to_design->modules_[prefix]->name = prefix;
- copy_to_design->modules_[prefix]->design = copy_to_design;
- copy_to_design->modules_[prefix]->attributes.erase("\\top");
+ RTLIL::Module *t = mod->clone();
+ t->name = prefix;
+ t->design = copy_to_design;
+ t->attributes.erase("\\top");
+ copy_to_design->add(t);
- queue.insert(copy_to_design->modules_[prefix]);
+ queue.insert(t);
done[mod->name] = prefix;
}
@@ -268,15 +270,16 @@ struct DesignPass : public Pass {
log("Importing %s as %s.\n", log_id(fmod), log_id(trg_name));
- if (copy_to_design->modules_.count(trg_name))
- delete copy_to_design->modules_.at(trg_name);
+ if (copy_to_design->module(trg_name) != nullptr)
+ copy_to_design->remove(copy_to_design->module(trg_name));
- copy_to_design->modules_[trg_name] = fmod->clone();
- copy_to_design->modules_[trg_name]->name = trg_name;
- copy_to_design->modules_[trg_name]->design = copy_to_design;
- copy_to_design->modules_[trg_name]->attributes.erase("\\top");
+ RTLIL::Module *t = fmod->clone();
+ t->name = trg_name;
+ t->design = copy_to_design;
+ t->attributes.erase("\\top");
+ copy_to_design->add(t);
- queue.insert(copy_to_design->modules_[trg_name]);
+ queue.insert(t);
done[cell->type] = trg_name;
}
@@ -294,12 +297,13 @@ struct DesignPass : public Pass {
{
std::string trg_name = as_name.empty() ? mod->name.str() : RTLIL::escape_id(as_name);
- if (copy_to_design->modules_.count(trg_name))
- delete copy_to_design->modules_.at(trg_name);
+ if (copy_to_design->module(trg_name) != nullptr)
+ copy_to_design->remove(copy_to_design->module(trg_name));
- copy_to_design->modules_[trg_name] = mod->clone();
- copy_to_design->modules_[trg_name]->name = trg_name;
- copy_to_design->modules_[trg_name]->design = copy_to_design;
+ RTLIL::Module *t = mod->clone();
+ t->name = trg_name;
+ t->design = copy_to_design;
+ copy_to_design->add(t);
}
}
@@ -307,8 +311,8 @@ struct DesignPass : public Pass {
{
RTLIL::Design *design_copy = new RTLIL::Design;
- for (auto &it : design->modules_)
- design_copy->add(it.second->clone());
+ for (auto mod : design->modules())
+ design_copy->add(mod->clone());
design_copy->selection_stack = design->selection_stack;
design_copy->selection_vars = design->selection_vars;
@@ -325,9 +329,8 @@ struct DesignPass : public Pass {
if (reset_mode || !load_name.empty() || push_mode || pop_mode)
{
- for (auto &it : design->modules_)
- delete it.second;
- design->modules_.clear();
+ for (auto mod : design->modules())
+ design->remove(mod);
design->selection_stack.clear();
design->selection_vars.clear();
@@ -346,15 +349,15 @@ struct DesignPass : public Pass {
delete node;
design->verilog_globals.clear();
- design->verilog_defines.clear();
+ design->verilog_defines->clear();
}
if (!load_name.empty() || pop_mode)
{
RTLIL::Design *saved_design = pop_mode ? pushed_designs.back() : saved_designs.at(load_name);
- for (auto &it : saved_design->modules_)
- design->add(it.second->clone());
+ for (auto mod : saved_design->modules())
+ design->add(mod->clone());
design->selection_stack = saved_design->selection_stack;
design->selection_vars = saved_design->selection_vars;
diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc
index cf3e46ace..8446e27b3 100644
--- a/passes/cmds/trace.cc
+++ b/passes/cmds/trace.cc
@@ -35,7 +35,7 @@ struct TraceMonitor : public RTLIL::Monitor
log("#TRACE# Module delete: %s\n", log_id(module));
}
- void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE
+ void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE
{
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
}
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index fa4a8ea29..3f4fe502d 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -42,11 +42,10 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
{
std::set<RTLIL::IdString> found_celltypes;
- for (auto i1 : design->modules_)
- for (auto i2 : i1.second->cells_)
+ for (auto mod : design->modules())
+ for (auto cell : mod->cells())
{
- RTLIL::Cell *cell = i2.second;
- if (design->has(cell->type))
+ if (design->module(cell->type) != nullptr)
continue;
if (cell->type.begins_with("$__"))
continue;
@@ -62,15 +61,15 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
std::map<RTLIL::IdString, int> portwidths;
log("Generate module for cell type %s:\n", celltype.c_str());
- for (auto i1 : design->modules_)
- for (auto i2 : i1.second->cells_)
- if (i2.second->type == celltype) {
- for (auto &conn : i2.second->connections()) {
+ for (auto mod : design->modules())
+ for (auto cell : mod->cells())
+ if (cell->type == celltype) {
+ for (auto &conn : cell->connections()) {
if (conn.first[0] != '$')
portnames.insert(conn.first);
portwidths[conn.first] = max(portwidths[conn.first], conn.second.size());
}
- for (auto &para : i2.second->parameters)
+ for (auto &para : cell->parameters)
parameters.insert(para.first);
}
@@ -168,26 +167,24 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// If any of the ports are actually interface ports, we will always need to
// reprocess the module:
if(!module->get_bool_attribute("\\interfaces_replaced_in_module")) {
- for (auto &wire : module->wires_) {
- if ((wire.second->port_input || wire.second->port_output) && wire.second->get_bool_attribute("\\is_interface"))
+ for (auto wire : module->wires()) {
+ if ((wire->port_input || wire->port_output) && wire->get_bool_attribute("\\is_interface"))
has_interface_ports = true;
}
}
// Always keep track of all derived interfaces available in the current module in 'interfaces_in_module':
dict<RTLIL::IdString, RTLIL::Module*> interfaces_in_module;
- for (auto &cell_it : module->cells_)
+ for (auto cell : module->cells())
{
- RTLIL::Cell *cell = cell_it.second;
if(cell->get_bool_attribute("\\is_interface")) {
- RTLIL::Module *intf_module = design->modules_[cell->type];
+ RTLIL::Module *intf_module = design->module(cell->type);
interfaces_in_module[cell->name] = intf_module;
}
}
- for (auto &cell_it : module->cells_)
+ for (auto cell : module->cells())
{
- RTLIL::Cell *cell = cell_it.second;
bool has_interfaces_not_found = false;
std::vector<RTLIL::IdString> connections_to_remove;
@@ -208,11 +205,11 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
dict<RTLIL::IdString, RTLIL::Module*> interfaces_to_add_to_submodule;
dict<RTLIL::IdString, RTLIL::IdString> modports_used_in_submodule;
- if (design->modules_.count(cell->type) == 0)
+ if (design->module(cell->type) == nullptr)
{
- if (design->modules_.count("$abstract" + cell->type.str()))
+ if (design->module("$abstract" + cell->type.str()) != nullptr)
{
- cell->type = design->modules_.at("$abstract" + cell->type.str())->derive(design, cell->parameters);
+ cell->type = design->module("$abstract" + cell->type.str())->derive(design, cell->parameters);
cell->parameters.clear();
did_something = true;
continue;
@@ -246,7 +243,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
continue;
loaded_module:
- if (design->modules_.count(cell->type) == 0)
+ if (design->module(cell->type) == nullptr)
log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str());
did_something = true;
} else {
@@ -256,7 +253,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// Go over all connections and see if any of them are SV interfaces. If they are, then add the replacements to
// some lists, so that the ports for sub-modules can be replaced further down:
for (auto &conn : cell->connections()) {
- if(mod->wires_.count(conn.first) != 0 && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list
+ if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list
//const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_type");
//for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness)
//}
@@ -285,11 +282,11 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
if (nexactmatch != 0) // Choose the one with the plain name if it exists
interface_name2 = interface_name;
RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name2);
- for (auto &mod_wire : mod_replace_ports->wires_) { // Go over all wires in interface, and add replacements to lists.
- std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire.first);
- std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire.first);
+ for (auto mod_wire : mod_replace_ports->wires()) { // Go over all wires in interface, and add replacements to lists.
+ std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire->name);
+ std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire);
connections_to_add_name.push_back(RTLIL::IdString(signal_name1));
- if(module->wires_.count(signal_name2) == 0) {
+ if(module->wire(signal_name2) == nullptr) {
log_error("Could not find signal '%s' in '%s'\n", signal_name2.c_str(), log_id(module->name));
}
else {
@@ -344,9 +341,9 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
}
}
- RTLIL::Module *mod = design->modules_[cell->type];
+ RTLIL::Module *mod = design->module(cell->type);
- if (design->modules_.at(cell->type)->get_blackbox_attribute()) {
+ if (design->module(cell->type)->get_blackbox_attribute()) {
if (flag_simcheck)
log_error("Module `%s' referenced in module `%s' in cell `%s' is a blackbox/whitebox module.\n",
cell->type.c_str(), module->name.c_str(), cell->name.c_str());
@@ -389,7 +386,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// an interface instance:
if (mod->get_bool_attribute("\\is_interface") && cell->get_bool_attribute("\\module_not_derived")) {
cell->set_bool_attribute("\\is_interface");
- RTLIL::Module *derived_module = design->modules_[cell->type];
+ RTLIL::Module *derived_module = design->module(cell->type);
interfaces_in_module[cell->name] = derived_module;
did_something = true;
}
@@ -414,25 +411,25 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
RTLIL::Cell *cell = it.first;
int idx = it.second.first, num = it.second.second;
- if (design->modules_.count(cell->type) == 0)
+ if (design->module(cell->type) == nullptr)
log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
- RTLIL::Module *mod = design->modules_[cell->type];
+ RTLIL::Module *mod = design->module(cell->type);
for (auto &conn : cell->connections_) {
int conn_size = conn.second.size();
RTLIL::IdString portname = conn.first;
if (portname.begins_with("$")) {
int port_id = atoi(portname.substr(1).c_str());
- for (auto &wire_it : mod->wires_)
- if (wire_it.second->port_id == port_id) {
- portname = wire_it.first;
+ for (auto wire : mod->wires())
+ if (wire->port_id == port_id) {
+ portname = wire->name;
break;
}
}
- if (mod->wires_.count(portname) == 0)
+ if (mod->wire(portname) == nullptr)
log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
- int port_size = mod->wires_.at(portname)->width;
+ int port_size = mod->wire(portname)->width;
if (conn_size == port_size || conn_size == 0)
continue;
if (conn_size != port_size*num)
@@ -470,21 +467,21 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
hierarchy_worker(design, used, top, 0);
std::vector<RTLIL::Module*> del_modules;
- for (auto &it : design->modules_)
- if (used.count(it.second) == 0)
- del_modules.push_back(it.second);
+ for (auto mod : design->modules())
+ if (used.count(mod) == 0)
+ del_modules.push_back(mod);
else {
// Now all interface ports must have been exploded, and it is hence
// safe to delete all of the remaining dummy interface ports:
pool<RTLIL::Wire*> del_wires;
- for(auto &wire : it.second->wires_) {
- if ((wire.second->port_input || wire.second->port_output) && wire.second->get_bool_attribute("\\is_interface")) {
- del_wires.insert(wire.second);
+ for(auto wire : mod->wires()) {
+ if ((wire->port_input || wire->port_output) && wire->get_bool_attribute("\\is_interface")) {
+ del_wires.insert(wire);
}
}
if (del_wires.size() > 0) {
- it.second->remove(del_wires);
- it.second->fixup_ports();
+ mod->remove(del_wires);
+ mod->fixup_ports();
}
}
@@ -493,9 +490,8 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
if (!purge_lib && mod->get_blackbox_attribute())
continue;
log("Removing unused module `%s'.\n", mod->name.c_str());
- design->modules_.erase(mod->name);
+ design->remove(mod);
del_counter++;
- delete mod;
}
log("Removed %d unused modules.\n", del_counter);
@@ -817,9 +813,9 @@ struct HierarchyPass : public Pass {
log_push();
if (top_mod == nullptr)
- for (auto &mod_it : design->modules_)
- if (mod_it.second->get_bool_attribute("\\top"))
- top_mod = mod_it.second;
+ for (auto mod : design->modules())
+ if (mod->get_bool_attribute("\\top"))
+ top_mod = mod;
if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
IdString top_name = top_mod->name.substr(strlen("$abstract"));
@@ -862,11 +858,11 @@ struct HierarchyPass : public Pass {
log_error("Design has no top module.\n");
if (top_mod != NULL) {
- for (auto &mod_it : design->modules_)
- if (mod_it.second == top_mod)
- mod_it.second->attributes["\\initial_top"] = RTLIL::Const(1);
+ for (auto mod : design->modules())
+ if (mod == top_mod)
+ mod->attributes["\\initial_top"] = RTLIL::Const(1);
else
- mod_it.second->attributes.erase("\\initial_top");
+ mod->attributes.erase("\\initial_top");
}
bool did_something = true;
@@ -900,9 +896,9 @@ struct HierarchyPass : public Pass {
// Delete modules marked as 'to_delete':
std::vector<RTLIL::Module *> modules_to_delete;
- for(auto &mod_it : design->modules_) {
- if (mod_it.second->get_bool_attribute("\\to_delete")) {
- modules_to_delete.push_back(mod_it.second);
+ for(auto mod : design->modules()) {
+ if (mod->get_bool_attribute("\\to_delete")) {
+ modules_to_delete.push_back(mod);
}
}
for(size_t i=0; i<modules_to_delete.size(); i++) {
@@ -917,12 +913,12 @@ struct HierarchyPass : public Pass {
}
if (top_mod != NULL) {
- for (auto &mod_it : design->modules_) {
- if (mod_it.second == top_mod)
- mod_it.second->attributes["\\top"] = RTLIL::Const(1);
+ for (auto mod : design->modules()) {
+ if (mod == top_mod)
+ mod->attributes["\\top"] = RTLIL::Const(1);
else
- mod_it.second->attributes.erase("\\top");
- mod_it.second->attributes.erase("\\initial_top");
+ mod->attributes.erase("\\top");
+ mod->attributes.erase("\\initial_top");
}
}
@@ -941,22 +937,20 @@ struct HierarchyPass : public Pass {
std::map<std::pair<RTLIL::Module*,int>, RTLIL::IdString> pos_map;
std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work;
- for (auto &mod_it : design->modules_)
- for (auto &cell_it : mod_it.second->cells_) {
- RTLIL::Cell *cell = cell_it.second;
- if (design->modules_.count(cell->type) == 0)
+ for (auto mod : design->modules())
+ for (auto cell : mod->cells()) {
+ if (design->module(cell->type) == nullptr)
continue;
for (auto &conn : cell->connections())
if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
- pos_mods.insert(design->modules_.at(cell->type));
- pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell));
+ pos_mods.insert(design->module(cell->type));
+ pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod, cell));
break;
}
}
for (auto module : pos_mods)
- for (auto &wire_it : module->wires_) {
- RTLIL::Wire *wire = wire_it.second;
+ for (auto wire : module->wires()) {
if (wire->port_id > 0)
pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = wire->name;
}
@@ -970,7 +964,7 @@ struct HierarchyPass : public Pass {
for (auto &conn : cell->connections())
if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
int id = atoi(conn.first.c_str()+1);
- std::pair<RTLIL::Module*,int> key(design->modules_.at(cell->type), id);
+ std::pair<RTLIL::Module*,int> key(design->module(cell->type), id);
if (pos_map.count(key) == 0) {
log(" Failed to map positional argument %d of cell %s.%s (%s).\n",
id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index eb912cfd4..b33882595 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -120,8 +120,8 @@ struct MemoryShareWorker
for (auto &cond : conditions) {
RTLIL::SigSpec sig1, sig2;
for (auto &it : cond) {
- sig1.append_bit(it.first);
- sig2.append_bit(it.second ? RTLIL::State::S1 : RTLIL::State::S0);
+ sig1.append(it.first);
+ sig2.append(it.second ? RTLIL::State::S1 : RTLIL::State::S0);
}
terms.append(module->Ne(NEW_ID, sig1, sig2));
created_conditions++;
@@ -284,8 +284,8 @@ struct MemoryShareWorker
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
if (groups.count(key) == 0) {
groups[key].first = grouped_bits.size();
- grouped_bits.append_bit(v_bits[i]);
- grouped_mask_bits.append_bit(v_mask_bits[i]);
+ grouped_bits.append(v_bits[i]);
+ grouped_mask_bits.append(v_mask_bits[i]);
}
groups[key].second.push_back(i);
}
@@ -295,7 +295,7 @@ struct MemoryShareWorker
for (int i = 0; i < bits.size(); i++) {
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
- result.append_bit(grouped_result.at(groups.at(key).first));
+ result.append(grouped_result.at(groups.at(key).first));
}
return result;
@@ -326,7 +326,7 @@ struct MemoryShareWorker
for (int i = 0; i < int(v_old_en.size()); i++) {
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]);
- new_merged_en.append_bit(grouped_new_en.at(groups.at(key)));
+ new_merged_en.append(grouped_new_en.at(groups.at(key)));
}
// Create the new merged_data signal.
@@ -635,8 +635,8 @@ struct MemoryShareWorker
for (int j = 0; j < int(this_en.size()); j++) {
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
if (!groups_en.count(key)) {
- grouped_last_en.append_bit(last_en[j]);
- grouped_this_en.append_bit(this_en[j]);
+ grouped_last_en.append(last_en[j]);
+ grouped_this_en.append(this_en[j]);
groups_en[key] = grouped_en->width;
grouped_en->width++;
}
@@ -665,11 +665,17 @@ struct MemoryShareWorker
// Setup and run
// -------------
- MemoryShareWorker(RTLIL::Design *design, RTLIL::Module *module) :
- design(design), module(module), sigmap(module)
+ MemoryShareWorker(RTLIL::Design *design) : design(design), modwalker(design) {}
+
+ void operator()(RTLIL::Module* module)
{
std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
+ this->module = module;
+ sigmap.set(module);
+ sig_to_mux.clear();
+ conditions_logic_cache.clear();
+
sigmap_xmux = sigmap;
for (auto cell : module->cells())
{
@@ -717,7 +723,7 @@ struct MemoryShareWorker
cone_ct.cell_types.erase("$shift");
cone_ct.cell_types.erase("$shiftx");
- modwalker.setup(design, module, &cone_ct);
+ modwalker.setup(module, &cone_ct);
for (auto &it : memindex)
consolidate_wr_using_sat(it.first, it.second.second);
@@ -755,8 +761,10 @@ struct MemorySharePass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n");
extra_args(args, 1, design);
+ MemoryShareWorker msw(design);
+
for (auto module : design->selected_modules())
- MemoryShareWorker(design, module);
+ msw(module);
}
} MemorySharePass;
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index cac265a52..07f9ee2a0 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -203,8 +203,8 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
return !(w2->port_input && w2->port_output);
if (w1->name[0] == '\\' && w2->name[0] == '\\') {
- if (regs.check_any(s1) != regs.check_any(s2))
- return regs.check_any(s2);
+ if (regs.check(s1) != regs.check(s2))
+ return regs.check(s2);
if (direct_wires.count(w1) != direct_wires.count(w2))
return direct_wires.count(w2) != 0;
if (conns.check_any(s1) != conns.check_any(s2))
@@ -358,8 +358,8 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
s2[i] = initval[i];
initval[i] = State::Sx;
}
- new_conn.first.append_bit(s1[i]);
- new_conn.second.append_bit(s2[i]);
+ new_conn.first.append(s1[i]);
+ new_conn.second.append(s2[i]);
}
if (new_conn.first.size() > 0) {
if (initval.is_fully_undef())
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 4a2f170b8..f9c5f68f2 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -31,9 +31,8 @@ PRIVATE_NAMESPACE_BEGIN
bool did_something;
-void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
+void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
{
- CellTypes ct(design);
SigMap sigmap(module);
SigPool driven_signals;
SigPool used_signals;
@@ -193,11 +192,11 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
for (auto &it : grouped_bits[i]) {
for (auto &bit : it.second) {
- new_conn.first.append_bit(bit);
- new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.size()));
+ new_conn.first.append(bit);
+ new_conn.second.append(RTLIL::SigBit(new_y, new_a.size()));
}
- new_a.append_bit(it.first.first);
- new_b.append_bit(it.first.second);
+ new_a.append(it.first.first);
+ new_b.append(it.first.second);
}
if (cell->type.in(ID($and), ID($or)) && i == GRP_CONST_A) {
@@ -496,6 +495,42 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
}
+ if (cell->type.in(ID($_XOR_), ID($_XNOR_)) || (cell->type.in(ID($xor), ID($xnor)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool()))
+ {
+ SigBit sig_a = assign_map(cell->getPort(ID::A));
+ SigBit sig_b = assign_map(cell->getPort(ID::B));
+ if (!sig_a.wire)
+ std::swap(sig_a, sig_b);
+ if (sig_b == State::S0 || sig_b == State::S1) {
+ if (cell->type.in(ID($xor), ID($_XOR_))) {
+ cover("opt.opt_expr.xor_buffer");
+ SigSpec sig_y;
+ if (cell->type == ID($xor))
+ sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a);
+ else if (cell->type == ID($_XOR_))
+ sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a);
+ else log_abort();
+ replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y);
+ goto next_cell;
+ }
+ if (cell->type.in(ID($xnor), ID($_XNOR_))) {
+ cover("opt.opt_expr.xnor_buffer");
+ SigSpec sig_y;
+ if (cell->type == ID($xnor)) {
+ sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit());
+ int width = cell->getParam(ID(Y_WIDTH)).as_int();
+ sig_y.append(RTLIL::Const(State::S1, width-1));
+ }
+ else if (cell->type == ID($_XNOR_))
+ sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a));
+ else log_abort();
+ replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_y);
+ goto next_cell;
+ }
+ log_abort();
+ }
+ }
+
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) &&
GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
{
@@ -651,10 +686,14 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
int i;
for (i = 0; i < GetSize(sig_y); i++) {
- if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx)
- module->connect(sig_y[i], sig_a[i]);
- else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx)
- module->connect(sig_y[i], sig_b[i]);
+ RTLIL::SigBit b = sig_b.at(i, State::Sx);
+ RTLIL::SigBit a = sig_a.at(i, State::Sx);
+ if (b == State::S0 && a != State::Sx)
+ module->connect(sig_y[i], a);
+ else if (sub && b == State::S1 && a == State::S1)
+ module->connect(sig_y[i], State::S0);
+ else if (!sub && a == State::S0 && b != State::Sx)
+ module->connect(sig_y[i], b);
else
break;
}
@@ -668,7 +707,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
}
- if (cell->type == "$alu")
+ if (cell->type == ID($alu))
{
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
@@ -678,9 +717,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_co = cell->getPort(ID(CO));
- if (sig_ci.wire || sig_bi.wire)
- goto next_cell;
-
bool sub = (sig_ci == State::S1 && sig_bi == State::S1);
// If not a subtraction, yet there is a carry or B is inverted
@@ -690,14 +726,21 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
int i;
for (i = 0; i < GetSize(sig_y); i++) {
- if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) {
- module->connect(sig_x[i], sub ? module->Not(NEW_ID, sig_a[i]).as_bit() : sig_a[i]);
+ RTLIL::SigBit b = sig_b.at(i, State::Sx);
+ RTLIL::SigBit a = sig_a.at(i, State::Sx);
+ if (b == State::S0 && a != State::Sx) {
module->connect(sig_y[i], sig_a[i]);
+ module->connect(sig_x[i], sub ? module->Not(NEW_ID, a).as_bit() : a);
module->connect(sig_co[i], sub ? State::S1 : State::S0);
}
- else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) {
- module->connect(sig_x[i], sig_b[i]);
- module->connect(sig_y[i], sig_b[i]);
+ else if (sub && b == State::S1 && a == State::S1) {
+ module->connect(sig_y[i], State::S0);
+ module->connect(sig_x[i], module->Not(NEW_ID, a));
+ module->connect(sig_co[i], State::S0);
+ }
+ else if (!sub && a == State::S0 && b != State::Sx) {
+ module->connect(sig_y[i], b);
+ module->connect(sig_x[i], b);
module->connect(sig_co[i], State::S0);
}
else
@@ -842,8 +885,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (input.match("11")) ACTION_DO_Y(0);
if (input.match(" *")) ACTION_DO_Y(x);
if (input.match("* ")) ACTION_DO_Y(x);
- if (input.match(" 0")) ACTION_DO(ID::Y, input.extract(1, 1));
- if (input.match("0 ")) ACTION_DO(ID::Y, input.extract(0, 1));
}
if (cell->type == ID($_MUX_)) {
@@ -1032,12 +1073,26 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
bool identity_wrt_b = false;
bool arith_inverse = false;
- if (cell->type.in(ID($add), ID($sub), ID($or), ID($xor)))
+ if (cell->type.in(ID($add), ID($sub), ID($alu), ID($or), ID($xor)))
{
RTLIL::SigSpec a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec b = assign_map(cell->getPort(ID::B));
- if (cell->type != ID($sub) && a.is_fully_const() && a.as_bool() == false)
+ bool sub = cell->type == ID($sub);
+
+ if (cell->type == ID($alu)) {
+ RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID(CI)));
+ RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID(BI)));
+
+ sub = (sig_ci == State::S1 && sig_bi == State::S1);
+
+ // If not a subtraction, yet there is a carry or B is inverted
+ // then no optimisation is possible as carry will not be constant
+ if (!sub && (sig_ci != State::S0 || sig_bi != State::S0))
+ goto next_cell;
+ }
+
+ if (!sub && a.is_fully_const() && a.as_bool() == false)
identity_wrt_b = true;
if (b.is_fully_const() && b.as_bool() == false)
@@ -1075,17 +1130,27 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (identity_wrt_a || identity_wrt_b)
{
if (identity_wrt_a)
- cover_list("opt.opt_expr.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
+ cover_list("opt.opt_expr.identwrt.a", "$add", "$sub", "$alu", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
if (identity_wrt_b)
- cover_list("opt.opt_expr.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
+ cover_list("opt.opt_expr.identwrt.b", "$add", "$sub", "$alu", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
+ if (cell->type == ID($alu)) {
+ int y_width = GetSize(cell->getPort(ID(Y)));
+ module->connect(cell->getPort(ID(X)), RTLIL::Const(State::S0, y_width));
+ module->connect(cell->getPort(ID(CO)), RTLIL::Const(State::S0, y_width));
+ cell->unsetPort(ID(BI));
+ cell->unsetPort(ID(CI));
+ cell->unsetPort(ID(X));
+ cell->unsetPort(ID(CO));
+ }
+
if (!identity_wrt_a) {
cell->setPort(ID::A, cell->getPort(ID::B));
- cell->parameters.at(ID(A_WIDTH)) = cell->parameters.at(ID(B_WIDTH));
- cell->parameters.at(ID(A_SIGNED)) = cell->parameters.at(ID(B_SIGNED));
+ cell->setParam(ID(A_WIDTH), cell->getParam(ID(B_WIDTH)));
+ cell->setParam(ID(A_SIGNED), cell->getParam(ID(B_SIGNED)));
}
cell->type = arith_inverse ? ID($neg) : ID($pos);
@@ -1590,7 +1655,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
int const_bit_set = get_highest_hot_index(const_sig);
- if(const_bit_set >= var_width)
+ if (const_bit_set >= var_width)
{
string cmp_name;
if (cmp_type == ID($lt) || cmp_type == ID($le))
@@ -1737,13 +1802,14 @@ struct OptExprPass : public Pass {
}
extra_args(args, argidx, design);
+ CellTypes ct(design);
for (auto module : design->selected_modules())
{
log("Optimizing module %s.\n", log_id(module));
if (undriven) {
did_something = false;
- replace_undriven(design, module);
+ replace_undriven(module, ct);
if (did_something)
design->scratchpad_set_bool("opt.did_something", true);
}
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 8823a9061..4aa78ff39 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -26,7 +26,6 @@
#include <stdio.h>
#include <set>
-#define USE_CELL_HASH_CACHE
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@@ -41,9 +40,7 @@ struct OptMergeWorker
CellTypes ct;
int total_count;
-#ifdef USE_CELL_HASH_CACHE
- dict<const RTLIL::Cell*, std::string> cell_hash_cache;
-#endif
+ SHA1 checksum;
static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
{
@@ -68,7 +65,6 @@ struct OptMergeWorker
}
}
-#ifdef USE_CELL_HASH_CACHE
std::string int_to_hash_string(unsigned int v)
{
if (v == 0)
@@ -83,14 +79,9 @@ struct OptMergeWorker
std::string hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
{
- if (cell_hash_cache.count(cell) > 0)
- return cell_hash_cache[cell];
-
+ vector<string> hash_conn_strings;
std::string hash_string = cell->type.str() + "\n";
- for (auto &it : cell->parameters)
- hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n";
-
const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
@@ -124,13 +115,22 @@ struct OptMergeWorker
conn = &alt_conn;
}
- vector<string> hash_conn_strings;
-
for (auto &it : *conn) {
- if (cell->output(it.first))
- continue;
- RTLIL::SigSpec sig = it.second;
- assign_map.apply(sig);
+ RTLIL::SigSpec sig;
+ if (cell->output(it.first)) {
+ if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
+ cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
+ cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
+ // For the 'Q' output of state elements,
+ // use its (* init *) attribute value
+ for (const auto &b : dff_init_map(it.second))
+ sig.append(b.wire ? State::Sx : b);
+ }
+ else
+ continue;
+ }
+ else
+ sig = assign_map(it.second);
string s = "C " + it.first.str() + "=";
for (auto &chunk : sig.chunks()) {
if (chunk.wire)
@@ -143,50 +143,59 @@ struct OptMergeWorker
hash_conn_strings.push_back(s + "\n");
}
+ for (auto &it : cell->parameters)
+ hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
+
std::sort(hash_conn_strings.begin(), hash_conn_strings.end());
for (auto it : hash_conn_strings)
hash_string += it;
- cell_hash_cache[cell] = sha1(hash_string);
- return cell_hash_cache[cell];
+ checksum.update(hash_string);
+ return checksum.final();
}
-#endif
- bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2, bool &lt)
+ bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
{
-#ifdef USE_CELL_HASH_CACHE
- std::string hash1 = hash_cell_parameters_and_connections(cell1);
- std::string hash2 = hash_cell_parameters_and_connections(cell2);
-
- if (hash1 != hash2) {
- lt = hash1 < hash2;
- return true;
- }
-#endif
-
- if (cell1->parameters != cell2->parameters) {
- std::map<RTLIL::IdString, RTLIL::Const> p1(cell1->parameters.begin(), cell1->parameters.end());
- std::map<RTLIL::IdString, RTLIL::Const> p2(cell2->parameters.begin(), cell2->parameters.end());
- lt = p1 < p2;
- return true;
- }
-
- dict<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections();
- dict<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
-
- for (auto &it : conn1) {
- if (cell1->output(it.first))
- it.second = RTLIL::SigSpec();
- else
- assign_map.apply(it.second);
- }
-
- for (auto &it : conn2) {
- if (cell2->output(it.first))
- it.second = RTLIL::SigSpec();
- else
- assign_map.apply(it.second);
+ log_assert(cell1 != cell2);
+ if (cell1->type != cell2->type) return false;
+
+ if (cell1->parameters != cell2->parameters)
+ return false;
+
+ if (cell1->connections_.size() != cell2->connections_.size())
+ return false;
+ for (const auto &it : cell1->connections_)
+ if (!cell2->connections_.count(it.first))
+ return false;
+
+ decltype(Cell::connections_) conn1, conn2;
+ conn1.reserve(cell1->connections_.size());
+ conn2.reserve(cell1->connections_.size());
+
+ for (const auto &it : cell1->connections_) {
+ if (cell1->output(it.first)) {
+ if (it.first == ID(Q) && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
+ cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
+ cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
+ // For the 'Q' output of state elements,
+ // use the (* init *) attribute value
+ auto &sig1 = conn1[it.first];
+ for (const auto &b : dff_init_map(it.second))
+ sig1.append(b.wire ? State::Sx : b);
+ auto &sig2 = conn2[it.first];
+ for (const auto &b : dff_init_map(cell2->getPort(it.first)))
+ sig2.append(b.wire ? State::Sx : b);
+ }
+ else {
+ conn1[it.first] = RTLIL::SigSpec();
+ conn2[it.first] = RTLIL::SigSpec();
+ }
+ }
+ else {
+ conn1[it.first] = assign_map(it.second);
+ conn2[it.first] = assign_map(cell2->getPort(it.first));
+ }
}
if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) ||
@@ -215,54 +224,9 @@ struct OptMergeWorker
sort_pmux_conn(conn2);
}
- if (conn1 != conn2) {
- std::map<RTLIL::IdString, RTLIL::SigSpec> c1(conn1.begin(), conn1.end());
- std::map<RTLIL::IdString, RTLIL::SigSpec> c2(conn2.begin(), conn2.end());
- lt = c1 < c2;
- return true;
- }
-
- if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
- cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
- cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
- std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
- std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
- for (size_t i = 0; i < q1.size(); i++)
- if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
- lt = q1.at(i) < q2.at(i);
- return true;
- }
- }
-
- return false;
+ return conn1 == conn2;
}
- bool compare_cells(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
- {
- if (cell1->type != cell2->type)
- return cell1->type < cell2->type;
-
- if ((!mode_share_all && !ct.cell_known(cell1->type)) || !cell1->known())
- return cell1 < cell2;
-
- if (cell1->has_keep_attr() || cell2->has_keep_attr())
- return cell1 < cell2;
-
- bool lt;
- if (compare_cell_parameters_and_connections(cell1, cell2, lt))
- return lt;
-
- return false;
- }
-
- struct CompareCells {
- OptMergeWorker *that;
- CompareCells(OptMergeWorker *that) : that(that) {}
- bool operator()(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const {
- return that->compare_cells(cell1, cell2);
- }
- };
-
OptMergeWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) :
design(design), module(module), assign_map(module), mode_share_all(mode_share_all)
{
@@ -299,9 +263,6 @@ struct OptMergeWorker
bool did_something = true;
while (did_something)
{
-#ifdef USE_CELL_HASH_CACHE
- cell_hash_cache.clear();
-#endif
std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells_.size());
for (auto &it : module->cells_) {
@@ -312,42 +273,51 @@ struct OptMergeWorker
}
did_something = false;
- std::map<RTLIL::Cell*, RTLIL::Cell*, CompareCells> sharemap(CompareCells(this));
+ dict<std::string, RTLIL::Cell*> sharemap;
for (auto cell : cells)
{
- if (sharemap.count(cell) > 0) {
- did_something = true;
- log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
- for (auto &it : cell->connections()) {
- if (cell->output(it.first)) {
- RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first);
- log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
- log_signal(it.second), log_signal(other_sig));
- module->connect(RTLIL::SigSig(it.second, other_sig));
- assign_map.add(it.second, other_sig);
-
- if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
- cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
- cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
- for (auto c : it.second.chunks()) {
- auto jt = c.wire->attributes.find(ID(init));
- if (jt == c.wire->attributes.end())
- continue;
- for (int i = c.offset; i < c.offset + c.width; i++)
- jt->second[i] = State::Sx;
+ if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known())
+ continue;
+
+ auto hash = hash_cell_parameters_and_connections(cell);
+ auto r = sharemap.insert(std::make_pair(hash, cell));
+ if (!r.second) {
+ if (compare_cell_parameters_and_connections(cell, r.first->second)) {
+ if (cell->has_keep_attr()) {
+ if (r.first->second->has_keep_attr())
+ continue;
+ std::swap(r.first->second, cell);
+ }
+
+
+ did_something = true;
+ log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), r.first->second->name.c_str());
+ for (auto &it : cell->connections()) {
+ if (cell->output(it.first)) {
+ RTLIL::SigSpec other_sig = r.first->second->getPort(it.first);
+ log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
+ log_signal(it.second), log_signal(other_sig));
+ module->connect(RTLIL::SigSig(it.second, other_sig));
+ assign_map.add(it.second, other_sig);
+
+ if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
+ cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
+ cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
+ for (auto c : it.second.chunks()) {
+ auto jt = c.wire->attributes.find(ID(init));
+ if (jt == c.wire->attributes.end())
+ continue;
+ for (int i = c.offset; i < c.offset + c.width; i++)
+ jt->second[i] = State::Sx;
+ }
+ dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
}
- dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
}
}
+ log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
+ module->remove(cell);
+ total_count++;
}
- log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
-#ifdef USE_CELL_HASH_CACHE
- cell_hash_cache.erase(cell);
-#endif
- module->remove(cell);
- total_count++;
- } else {
- sharemap[cell] = cell;
}
}
}
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index f74655d1c..fd734c387 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -192,13 +192,13 @@ struct OptReduceWorker
if (all_tuple_bits_same)
{
- old_sig_conn.first.append_bit(sig_y.at(i));
- old_sig_conn.second.append_bit(sig_a.at(i));
+ old_sig_conn.first.append(sig_y.at(i));
+ old_sig_conn.second.append(sig_a.at(i));
}
else if (consolidated_in_tuples_map.count(in_tuple))
{
- old_sig_conn.first.append_bit(sig_y.at(i));
- old_sig_conn.second.append_bit(consolidated_in_tuples_map.at(in_tuple));
+ old_sig_conn.first.append(sig_y.at(i));
+ old_sig_conn.second.append(consolidated_in_tuples_map.at(in_tuple));
}
else
{
diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc
index 92b5794ac..a7fefc291 100644
--- a/passes/opt/pmux2shiftx.cc
+++ b/passes/opt/pmux2shiftx.cc
@@ -331,7 +331,7 @@ struct Pmux2ShiftxPass : public Pass {
pair<SigSpec, Const> entry;
for (auto it : bits) {
- entry.first.append_bit(it.first);
+ entry.first.append(it.first);
entry.second.bits.push_back(it.second);
}
@@ -352,7 +352,7 @@ struct Pmux2ShiftxPass : public Pass {
pair<SigSpec, Const> entry;
for (auto it : bits) {
- entry.first.append_bit(it.first);
+ entry.first.append(it.first);
entry.second.bits.push_back(it.second);
}
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 92ce3fd11..c11381138 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -41,7 +41,8 @@ struct ShareWorkerConfig
struct ShareWorker
{
- ShareWorkerConfig config;
+ const ShareWorkerConfig config;
+ int limit;
pool<RTLIL::IdString> generic_ops;
RTLIL::Design *design;
@@ -49,7 +50,6 @@ struct ShareWorker
CellTypes fwd_ct, cone_ct;
ModWalker modwalker;
- ModIndex mi;
pool<RTLIL::Cell*> cells_to_remove;
pool<RTLIL::Cell*> recursion_state;
@@ -516,7 +516,7 @@ struct ShareWorker
if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
- new_a.append_bit(RTLIL::State::S0);
+ new_a.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::A, new_a);
}
unsigned_cell->parameters.at(ID(A_SIGNED)) = true;
@@ -588,7 +588,7 @@ struct ShareWorker
if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
- new_a.append_bit(RTLIL::State::S0);
+ new_a.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::A, new_a);
}
unsigned_cell->parameters.at(ID(A_SIGNED)) = true;
@@ -601,7 +601,7 @@ struct ShareWorker
if (unsigned_cell->getPort(ID::B).to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at(ID(B_WIDTH)) = unsigned_cell->parameters.at(ID(B_WIDTH)).as_int() + 1;
RTLIL::SigSpec new_b = unsigned_cell->getPort(ID::B);
- new_b.append_bit(RTLIL::State::S0);
+ new_b.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::B, new_b);
}
unsigned_cell->parameters.at(ID(B_SIGNED)) = true;
@@ -790,7 +790,7 @@ struct ShareWorker
p.second.bits.clear();
for (auto &it : p_bits) {
- p.first.append_bit(it.first);
+ p.first.append(it.first);
p.second.bits.push_back(it.second);
}
@@ -906,14 +906,14 @@ struct ShareWorker
if (used_in_a)
for (auto p : c_patterns) {
for (int i = 0; i < GetSize(sig_s); i++)
- p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0);
+ p.first.append(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0);
if (sort_check_activation_pattern(p))
activation_patterns_cache[cell].insert(p);
}
for (int idx : used_in_b_parts)
for (auto p : c_patterns) {
- p.first.append_bit(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1);
+ p.first.append(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1);
if (sort_check_activation_pattern(p))
activation_patterns_cache[cell].insert(p);
}
@@ -948,7 +948,7 @@ struct ShareWorker
RTLIL::SigSpec signal;
for (auto &bit : all_bits)
- signal.append_bit(bit);
+ signal.append(bit);
return signal;
}
@@ -963,7 +963,7 @@ struct ShareWorker
for (int i = 0; i < GetSize(p_first); i++)
if (filter_bits.count(p_first[i]) == 0) {
- new_p.first.append_bit(p_first[i]);
+ new_p.first.append(p_first[i]);
new_p.second.bits.push_back(p.second.bits.at(i));
}
@@ -1071,6 +1071,8 @@ struct ShareWorker
ct.setup_internals();
ct.setup_stdcells();
+ ModIndex mi(module);
+
pool<RTLIL::Cell*> queue, covered;
queue.insert(cell);
@@ -1117,13 +1119,9 @@ struct ShareWorker
module->remove(cell);
}
- ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) :
- config(config), design(design), module(module), mi(module)
+ ShareWorker(ShareWorkerConfig config, RTLIL::Design* design) :
+ config(config), design(design), modwalker(design)
{
- #ifndef NDEBUG
- bool before_scc = module_has_scc();
- #endif
-
generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end());
generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end());
generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end());
@@ -1140,8 +1138,27 @@ struct ShareWorker
cone_ct.cell_types.erase(ID($shr));
cone_ct.cell_types.erase(ID($sshl));
cone_ct.cell_types.erase(ID($sshr));
+ }
- modwalker.setup(design, module);
+ void operator()(RTLIL::Module *module) {
+ this->module = module;
+
+ #ifndef NDEBUG
+ bool before_scc = module_has_scc();
+ #endif
+
+ limit = config.limit;
+ modwalker.setup(module);
+
+ cells_to_remove.clear();
+ recursion_state.clear();
+ topo_cell_drivers.clear();
+ topo_bit_drivers.clear();
+ exclusive_ctrls.clear();
+ terminal_bits.clear();
+ shareable_cells.clear();
+ forbidden_controls_cache.clear();
+ activation_patterns_cache.clear();
find_terminal_bits();
find_shareable_cells();
@@ -1399,8 +1416,8 @@ struct ShareWorker
topo_cell_drivers[cell] = { supercell };
topo_cell_drivers[other_cell] = { supercell };
- if (config.limit > 0)
- config.limit--;
+ if (limit > 0)
+ limit--;
break;
}
@@ -1528,9 +1545,10 @@ struct SharePass : public Pass {
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second))
- ShareWorker(config, design, mod_it.second);
+ ShareWorker sw(config, design);
+
+ for (auto module : design->selected_modules())
+ sw(module);
}
} SharePass;
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 04b882db9..b5451849d 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -98,7 +98,7 @@ struct WreduceWorker
SigSpec sig_removed;
for (int i = GetSize(bits_removed)-1; i >= 0; i--)
- sig_removed.append_bit(bits_removed[i]);
+ sig_removed.append(bits_removed[i]);
if (GetSize(bits_removed) == GetSize(sig_y)) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc
index d4aee9df0..caf938a74 100644
--- a/passes/proc/proc_prune.cc
+++ b/passes/proc/proc_prune.cc
@@ -93,7 +93,7 @@ struct PruneWorker
for (int i = 0; i < GetSize(lhs); i++) {
RTLIL::SigBit lhs_bit = lhs[i];
if (lhs_bit.wire && !assigned[lhs_bit]) {
- conn.first.append_bit(lhs_bit);
+ conn.first.append(lhs_bit);
conn.second.append(rhs.extract(i));
}
}
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index f9e7783a9..24aba22f3 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -117,11 +117,11 @@ struct Clk2fflogicPass : public Pass {
SigSpec clock_edge_pattern;
if (clkpol) {
- clock_edge_pattern.append_bit(State::S0);
- clock_edge_pattern.append_bit(State::S1);
+ clock_edge_pattern.append(State::S0);
+ clock_edge_pattern.append(State::S1);
} else {
- clock_edge_pattern.append_bit(State::S1);
- clock_edge_pattern.append_bit(State::S0);
+ clock_edge_pattern.append(State::S1);
+ clock_edge_pattern.append(State::S0);
}
SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
@@ -257,11 +257,11 @@ struct Clk2fflogicPass : public Pass {
SigSpec clock_edge_pattern;
if (clkpol) {
- clock_edge_pattern.append_bit(State::S0);
- clock_edge_pattern.append_bit(State::S1);
+ clock_edge_pattern.append(State::S0);
+ clock_edge_pattern.append(State::S1);
} else {
- clock_edge_pattern.append_bit(State::S1);
- clock_edge_pattern.append_bit(State::S0);
+ clock_edge_pattern.append(State::S1);
+ clock_edge_pattern.append(State::S0);
}
SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index e0bb439f4..148480d55 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -88,25 +88,24 @@ struct BruteForceEquivChecker
mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
{
log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
- for (auto &w : mod1->wires_)
+ for (auto w : mod1->wires())
{
- RTLIL::Wire *wire1 = w.second;
- if (wire1->port_id == 0)
+ if (w->port_id == 0)
continue;
- if (mod2->wires_.count(wire1->name) == 0)
- log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", wire1->name.c_str());
+ if (mod2->wire(w->name) == nullptr)
+ log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", w->name.c_str());
- RTLIL::Wire *wire2 = mod2->wires_.at(wire1->name);
- if (wire1->width != wire2->width || wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output)
- log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", wire1->name.c_str());
+ RTLIL::Wire *w2 = mod2->wire(w->name);
+ if (w->width != w2->width || w->port_input != w2->port_input || w->port_output != w2->port_output)
+ log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", w->name.c_str());
- if (wire1->port_input) {
- mod1_inputs.append(wire1);
- mod2_inputs.append(wire2);
+ if (w->port_input) {
+ mod1_inputs.append(w);
+ mod2_inputs.append(w2);
} else {
- mod1_outputs.append(wire1);
- mod2_outputs.append(wire2);
+ mod1_outputs.append(w);
+ mod2_outputs.append(w2);
}
}
@@ -148,17 +147,17 @@ struct VlogHammerReporter
SatGen satgen(ez.get(), &sigmap);
satgen.model_undef = model_undef;
- for (auto &c : module->cells_)
- if (!satgen.importCell(c.second))
- log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
+ for (auto c : module->cells())
+ if (!satgen.importCell(c))
+ log_error("Failed to import cell %s (type %s) to SAT database.\n", log_id(c->name), log_id(c->type));
ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
- std::vector<int> y_vec = satgen.importDefSigSpec(module->wires_.at("\\y"));
+ std::vector<int> y_vec = satgen.importDefSigSpec(module->wire("\\y"));
std::vector<bool> y_values;
if (model_undef) {
- std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wires_.at("\\y"));
+ std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire("\\y"));
y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end());
}
@@ -253,7 +252,7 @@ struct VlogHammerReporter
std::vector<RTLIL::State> bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width);
for (int i = 0; i < int(inputs.size()); i++) {
- RTLIL::Wire *wire = module->wires_.at(inputs[i]);
+ RTLIL::Wire *wire = module->wire(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
@@ -263,21 +262,21 @@ struct VlogHammerReporter
if (module == modules.front()) {
RTLIL::SigSpec sig(wire);
if (!ce.eval(sig))
- log_error("Can't read back value for port %s!\n", RTLIL::id2cstr(inputs[i]));
+ log_error("Can't read back value for port %s!\n", log_id(inputs[i]));
input_pattern_list += stringf(" %s", sig.as_const().as_string().c_str());
- log("++PAT++ %d %s %s #\n", idx, RTLIL::id2cstr(inputs[i]), sig.as_const().as_string().c_str());
+ log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string().c_str());
}
}
- if (module->wires_.count("\\y") == 0)
- log_error("No output wire (y) found in module %s!\n", RTLIL::id2cstr(module->name));
+ if (module->wire("\\y") == nullptr)
+ log_error("No output wire (y) found in module %s!\n", log_id(module->name));
- RTLIL::SigSpec sig(module->wires_.at("\\y"));
+ RTLIL::SigSpec sig(module->wire("\\y"));
RTLIL::SigSpec undef;
while (!ce.eval(sig, undef)) {
- // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef));
- log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
+ // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", log_id(module->name), log_signal(sig), log_signal(undef));
+ log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), log_id(module->name));
ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
}
@@ -289,7 +288,7 @@ struct VlogHammerReporter
sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
} else if (rtl_sig.size() > 0) {
if (rtl_sig.size() != sig.size())
- log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
+ log_error("Output (y) has a different width in module %s compared to rtl!\n", log_id(module->name));
for (int i = 0; i < GetSize(sig); i++)
if (rtl_sig[i] == RTLIL::State::Sx)
sig[i] = RTLIL::State::Sx;
@@ -307,10 +306,10 @@ struct VlogHammerReporter
{
for (auto name : split(module_list, ",")) {
RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name);
- if (design->modules_.count(esc_name) == 0)
+ if (design->module(esc_name) == nullptr)
log_error("Can't find module %s in current design!\n", name.c_str());
log("Using module %s (%s).\n", esc_name.c_str(), name.c_str());
- modules.push_back(design->modules_.at(esc_name));
+ modules.push_back(design->module(esc_name));
module_names.push_back(name);
}
@@ -319,11 +318,11 @@ struct VlogHammerReporter
int width = -1;
RTLIL::IdString esc_name = RTLIL::escape_id(name);
for (auto mod : modules) {
- if (mod->wires_.count(esc_name) == 0)
- log_error("Can't find input %s in module %s!\n", name.c_str(), RTLIL::id2cstr(mod->name));
- RTLIL::Wire *port = mod->wires_.at(esc_name);
+ if (mod->wire(esc_name) == nullptr)
+ log_error("Can't find input %s in module %s!\n", name.c_str(), log_id(mod->name));
+ RTLIL::Wire *port = mod->wire(esc_name);
if (!port->port_input || port->port_output)
- log_error("Wire %s in module %s is not an input!\n", name.c_str(), RTLIL::id2cstr(mod->name));
+ log_error("Wire %s in module %s is not an input!\n", name.c_str(), log_id(mod->name));
if (width >= 0 && width != port->width)
log_error("Port %s has different sizes in the different modules!\n", name.c_str());
width = port->width;
@@ -415,11 +414,11 @@ struct EvalPass : public Pass {
/* this should only be used for regression testing of ConstEval -- see vloghammer */
std::string mod1_name = RTLIL::escape_id(args[++argidx]);
std::string mod2_name = RTLIL::escape_id(args[++argidx]);
- if (design->modules_.count(mod1_name) == 0)
+ if (design->module(mod1_name) == nullptr)
log_error("Can't find module `%s'!\n", mod1_name.c_str());
- if (design->modules_.count(mod2_name) == 0)
+ if (design->module(mod2_name) == nullptr)
log_error("Can't find module `%s'!\n", mod2_name.c_str());
- BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
+ BruteForceEquivChecker checker(design->module(mod1_name), design->module(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
if (checker.errors > 0)
log_cmd_error("Modules are not equivalent!\n");
log("Verified %s = %s (using brute-force check on %d cases).\n",
@@ -441,13 +440,12 @@ struct EvalPass : public Pass {
extra_args(args, argidx, design);
RTLIL::Module *module = NULL;
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second)) {
- if (module)
- log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
- RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first));
- module = mod_it.second;
- }
+ for (auto mod : design->selected_modules()) {
+ if (module)
+ log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
+ log_id(module->name), log_id(mod->name));
+ module = mod;
+ }
if (module == NULL)
log_cmd_error("Can't perform EVAL on an empty selection!\n");
@@ -468,9 +466,9 @@ struct EvalPass : public Pass {
}
if (shows.size() == 0) {
- for (auto &it : module->wires_)
- if (it.second->port_output)
- shows.push_back(it.second->name.str());
+ for (auto w : module->wires())
+ if (w->port_output)
+ shows.push_back(w->name.str());
}
if (tables.empty())
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 29dfc7b19..8fb47f357 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -53,7 +53,7 @@ bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells,
{
if (cell->name[0] == '$' || dff_cells.count(cell->name))
return false;
- if (cell->type[0] == '\\' && !design->modules_.count(cell->type))
+ if (cell->type[0] == '\\' && (design->module(cell->type) == nullptr))
return false;
return true;
}
@@ -85,27 +85,24 @@ void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
SigMap sigmap(module);
SigPool dffsignals;
- for (auto &it : module->cells_) {
- if (ct.cell_known(it.second->type) && it.second->hasPort("\\Q"))
- dffsignals.add(sigmap(it.second->getPort("\\Q")));
+ for (auto cell : module->cells()) {
+ if (ct.cell_known(cell->type) && cell->hasPort("\\Q"))
+ dffsignals.add(sigmap(cell->getPort("\\Q")));
}
- for (auto &it : module->wires_) {
- if (dffsignals.check_any(it.second))
- dff_wires.insert(it.first);
+ for (auto w : module->wires()) {
+ if (dffsignals.check_any(w))
+ dff_wires.insert(w->name);
}
}
-void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module)
+void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Module *module)
{
std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info;
SigMap sigmap(module);
- for (auto &it : module->cells_)
+ for (auto cell : module->selected_cells())
{
- if (!design->selected(module, it.second))
- continue;
-
dff_map_bit_info_t info;
info.bit_d = RTLIL::State::Sm;
info.bit_clk = RTLIL::State::Sm;
@@ -113,7 +110,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
info.clk_polarity = false;
info.arst_polarity = false;
info.arst_value = RTLIL::State::Sm;
- info.cell = it.second;
+ info.cell = cell;
if (info.cell->type == "$dff") {
info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
@@ -164,12 +161,12 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
}
std::map<RTLIL::IdString, dff_map_info_t> empty_dq_map;
- for (auto &it : module->wires_)
+ for (auto w : module->wires())
{
- if (!consider_wire(it.second, empty_dq_map))
+ if (!consider_wire(w, empty_dq_map))
continue;
- std::vector<RTLIL::SigBit> bits_q = sigmap(it.second).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> bits_q = sigmap(w).to_sigbit_vector();
std::vector<RTLIL::SigBit> bits_d;
std::vector<RTLIL::State> arst_value;
std::set<RTLIL::Cell*> cells;
@@ -207,7 +204,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
info.arst_value = arst_value;
for (auto it : cells)
info.cells.push_back(it->name);
- map[it.first] = info;
+ map[w->name] = info;
}
}
@@ -314,26 +311,23 @@ struct ExposePass : public Pass {
RTLIL::Module *first_module = NULL;
std::set<RTLIL::IdString> shared_dff_wires;
- for (auto &mod_it : design->modules_)
+ for (auto mod : design->selected_modules())
{
- if (!design->selected(mod_it.second))
- continue;
-
- create_dff_dq_map(dff_dq_maps[mod_it.second], design, mod_it.second);
+ create_dff_dq_map(dff_dq_maps[mod], mod);
if (!flag_shared)
continue;
if (first_module == NULL) {
- for (auto &it : dff_dq_maps[mod_it.second])
+ for (auto &it : dff_dq_maps[mod])
shared_dff_wires.insert(it.first);
- first_module = mod_it.second;
+ first_module = mod;
} else {
std::set<RTLIL::IdString> new_shared_dff_wires;
for (auto &it : shared_dff_wires) {
- if (!dff_dq_maps[mod_it.second].count(it))
+ if (!dff_dq_maps[mod].count(it))
continue;
- if (!compare_wires(first_module->wires_.at(it), mod_it.second->wires_.at(it)))
+ if (!compare_wires(first_module->wire(it), mod->wire(it)))
continue;
new_shared_dff_wires.insert(it);
}
@@ -364,28 +358,23 @@ struct ExposePass : public Pass {
{
RTLIL::Module *first_module = NULL;
- for (auto &mod_it : design->modules_)
+ for (auto module : design->selected_modules())
{
- RTLIL::Module *module = mod_it.second;
-
- if (!design->selected(module))
- continue;
-
std::set<RTLIL::IdString> dff_wires;
if (flag_dff)
find_dff_wires(dff_wires, module);
if (first_module == NULL)
{
- for (auto &it : module->wires_)
- if (design->selected(module, it.second) && consider_wire(it.second, dff_dq_maps[module]))
- if (!flag_dff || dff_wires.count(it.first))
- shared_wires.insert(it.first);
+ for (auto w : module->wires())
+ if (design->selected(module, w) && consider_wire(w, dff_dq_maps[module]))
+ if (!flag_dff || dff_wires.count(w->name))
+ shared_wires.insert(w->name);
if (flag_evert)
- for (auto &it : module->cells_)
- if (design->selected(module, it.second) && consider_cell(design, dff_cells[module], it.second))
- shared_cells.insert(it.first);
+ for (auto cell : module->cells())
+ if (design->selected(module, cell) && consider_cell(design, dff_cells[module], cell))
+ shared_cells.insert(cell->name);
first_module = module;
}
@@ -397,16 +386,16 @@ struct ExposePass : public Pass {
{
RTLIL::Wire *wire;
- if (module->wires_.count(it) == 0)
+ if (module->wire(it) == nullptr)
goto delete_shared_wire;
- wire = module->wires_.at(it);
+ wire = module->wire(it);
if (!design->selected(module, wire))
goto delete_shared_wire;
if (!consider_wire(wire, dff_dq_maps[module]))
goto delete_shared_wire;
- if (!compare_wires(first_module->wires_.at(it), wire))
+ if (!compare_wires(first_module->wire(it), wire))
goto delete_shared_wire;
if (flag_dff && !dff_wires.count(it))
goto delete_shared_wire;
@@ -421,16 +410,16 @@ struct ExposePass : public Pass {
{
RTLIL::Cell *cell;
- if (module->cells_.count(it) == 0)
+ if (module->cell(it) == nullptr)
goto delete_shared_cell;
- cell = module->cells_.at(it);
+ cell = module->cell(it);
if (!design->selected(module, cell))
goto delete_shared_cell;
if (!consider_cell(design, dff_cells[module], cell))
goto delete_shared_cell;
- if (!compare_cells(first_module->cells_.at(it), cell))
+ if (!compare_cells(first_module->cell(it), cell))
goto delete_shared_cell;
if (0)
@@ -446,13 +435,8 @@ struct ExposePass : public Pass {
}
}
- for (auto &mod_it : design->modules_)
+ for (auto module : design->selected_modules())
{
- RTLIL::Module *module = mod_it.second;
-
- if (!design->selected(module))
- continue;
-
std::set<RTLIL::IdString> dff_wires;
if (flag_dff && !flag_shared)
find_dff_wires(dff_wires, module);
@@ -461,49 +445,49 @@ struct ExposePass : public Pass {
SigMap out_to_in_map;
- for (auto &it : module->wires_)
+ for (auto w : module->wires())
{
if (flag_shared) {
- if (shared_wires.count(it.first) == 0)
+ if (shared_wires.count(w->name) == 0)
continue;
} else {
- if (!design->selected(module, it.second) || !consider_wire(it.second, dff_dq_maps[module]))
+ if (!design->selected(module, w) || !consider_wire(w, dff_dq_maps[module]))
continue;
- if (flag_dff && !dff_wires.count(it.first))
+ if (flag_dff && !dff_wires.count(w->name))
continue;
}
if (flag_input)
{
- if (!it.second->port_input) {
- it.second->port_input = true;
- log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name));
- RTLIL::Wire *w = module->addWire(NEW_ID, GetSize(it.second));
- out_to_in_map.add(it.second, w);
+ if (!w->port_input) {
+ w->port_input = true;
+ log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
+ RTLIL::Wire *in_wire = module->addWire(NEW_ID, GetSize(w));
+ out_to_in_map.add(w, in_wire);
}
}
else
{
- if (!it.second->port_output) {
- it.second->port_output = true;
- log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name));
+ if (!w->port_output) {
+ w->port_output = true;
+ log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
}
if (flag_cut) {
- RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width);
+ RTLIL::Wire *in_wire = add_new_wire(module, w->name.str() + sep + "i", w->width);
in_wire->port_input = true;
- out_to_in_map.add(sigmap(it.second), in_wire);
+ out_to_in_map.add(sigmap(w), in_wire);
}
}
}
if (flag_input)
{
- for (auto &it : module->cells_) {
- if (!ct.cell_known(it.second->type))
+ for (auto cell : module->cells()) {
+ if (!ct.cell_known(cell->type))
continue;
- for (auto &conn : it.second->connections_)
- if (ct.cell_output(it.second->type, conn.first))
+ for (auto &conn : cell->connections_)
+ if (ct.cell_output(cell->type, conn.first))
conn.second = out_to_in_map(sigmap(conn.second));
}
@@ -513,11 +497,11 @@ struct ExposePass : public Pass {
if (flag_cut)
{
- for (auto &it : module->cells_) {
- if (!ct.cell_known(it.second->type))
+ for (auto cell : module->cells()) {
+ if (!ct.cell_known(cell->type))
continue;
- for (auto &conn : it.second->connections_)
- if (ct.cell_input(it.second->type, conn.first))
+ for (auto &conn : cell->connections_)
+ if (ct.cell_input(cell->type, conn.first))
conn.second = out_to_in_map(sigmap(conn.second));
}
@@ -529,10 +513,10 @@ struct ExposePass : public Pass {
for (auto &dq : dff_dq_maps[module])
{
- if (!module->wires_.count(dq.first))
+ if (module->wire(dq.first) == nullptr)
continue;
- RTLIL::Wire *wire = module->wires_.at(dq.first);
+ RTLIL::Wire *wire = module->wire(dq.first);
std::set<RTLIL::SigBit> wire_bits_set = sigmap(wire).to_sigbit_set();
std::vector<RTLIL::SigBit> wire_bits_vec = sigmap(wire).to_sigbit_vector();
@@ -541,7 +525,7 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0);
for (auto &cell_name : info.cells) {
- RTLIL::Cell *cell = module->cells_.at(cell_name);
+ RTLIL::Cell *cell = module->cell(cell_name);
std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort("\\Q")).to_sigbit_vector();
for (auto &bit : cell_q_bits)
if (wire_bits_set.count(bit))
@@ -609,25 +593,22 @@ struct ExposePass : public Pass {
{
std::vector<RTLIL::Cell*> delete_cells;
- for (auto &it : module->cells_)
+ for (auto cell : module->cells())
{
if (flag_shared) {
- if (shared_cells.count(it.first) == 0)
+ if (shared_cells.count(cell->name) == 0)
continue;
} else {
- if (!design->selected(module, it.second) || !consider_cell(design, dff_cells[module], it.second))
+ if (!design->selected(module, cell) || !consider_cell(design, dff_cells[module], cell))
continue;
}
- RTLIL::Cell *cell = it.second;
-
- if (design->modules_.count(cell->type))
+ if (design->module(cell->type) != nullptr)
{
- RTLIL::Module *mod = design->modules_.at(cell->type);
+ RTLIL::Module *mod = design->module(cell->type);
- for (auto &it : mod->wires_)
+ for (auto p : mod->wires())
{
- RTLIL::Wire *p = it.second;
if (!p->port_input && !p->port_output)
continue;
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index f29631639..54016e528 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -614,29 +614,29 @@ struct FreduceWorker
int bits_full_total = 0;
std::vector<std::set<RTLIL::SigBit>> batches;
- for (auto &it : module->wires_)
- if (it.second->port_input) {
- batches.push_back(sigmap(it.second).to_sigbit_set());
- bits_full_total += it.second->width;
+ for (auto w : module->wires())
+ if (w->port_input) {
+ batches.push_back(sigmap(w).to_sigbit_set());
+ bits_full_total += w->width;
}
- for (auto &it : module->cells_) {
- if (ct.cell_known(it.second->type)) {
+ for (auto cell : module->cells()) {
+ if (ct.cell_known(cell->type)) {
std::set<RTLIL::SigBit> inputs, outputs;
- for (auto &port : it.second->connections()) {
+ for (auto &port : cell->connections()) {
std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
- if (ct.cell_output(it.second->type, port.first))
+ if (ct.cell_output(cell->type, port.first))
outputs.insert(bits.begin(), bits.end());
else
inputs.insert(bits.begin(), bits.end());
}
- std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(it.second, inputs);
+ std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(cell, inputs);
for (auto &bit : outputs)
drivers[bit] = drv;
batches.push_back(outputs);
bits_full_total += outputs.size();
}
- if (inv_mode && it.second->type == "$_NOT_")
- inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y"))));
+ if (inv_mode && cell->type == "$_NOT_")
+ inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\Y"))));
}
int bits_count = 0;
@@ -828,10 +828,8 @@ struct FreducePass : public Pass {
extra_args(args, argidx, design);
int bitcount = 0;
- for (auto &mod_it : design->modules_) {
- RTLIL::Module *module = mod_it.second;
- if (design->selected(module))
- bitcount += FreduceWorker(design, module).run();
+ for (auto module : design->selected_modules()) {
+ bitcount += FreduceWorker(design, module).run();
}
log("Rewired a total of %d signal bits.\n", bitcount);
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
index 11cfddcd9..92c52398c 100644
--- a/passes/techmap/extract_reduce.cc
+++ b/passes/techmap/extract_reduce.cc
@@ -286,7 +286,7 @@ struct ExtractReducePass : public Pass
SigSpec input;
for (auto b : input_pool)
if (input_pool_intermed.count(b) == 0)
- input.append_bit(b);
+ input.append(b);
SigBit output = sigmap(head_cell->getPort(ID::Y)[0]);
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index a2ad87f7d..427b72a6a 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -1405,7 +1405,7 @@ struct FlowmapWorker
RTLIL::SigSpec lut_a, lut_y = node;
for (auto input_node : input_nodes)
- lut_a.append_bit(input_node);
+ lut_a.append(input_node);
lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size()));
RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table);
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 10001baaa..0a67d9dbe 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -906,8 +906,8 @@ struct TechmapWorker
RTLIL::SigSig port_conn;
for (auto &it : port_connmap) {
- port_conn.first.append_bit(it.first);
- port_conn.second.append_bit(it.second);
+ port_conn.first.append(it.first);
+ port_conn.second.append(it.second);
}
tpl->connect(port_conn);
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-10 21:35:57 +0000