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-rw-r--r--passes/cmds/Makefile.inc1
-rw-r--r--passes/cmds/add.cc4
-rw-r--r--passes/cmds/design.cc3
-rw-r--r--passes/cmds/exec.cc205
-rw-r--r--passes/cmds/select.cc61
-rw-r--r--passes/fsm/fsm_extract.cc6
-rw-r--r--passes/sat/eval.cc90
-rw-r--r--passes/sat/freduce.cc28
-rw-r--r--passes/sat/miter.cc116
-rw-r--r--passes/techmap/iopadmap.cc24
-rw-r--r--passes/techmap/techmap.cc2
11 files changed, 394 insertions, 146 deletions
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 20b38bf8e..60f20fa6d 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -1,4 +1,5 @@
+OBJS += passes/cmds/exec.o
OBJS += passes/cmds/add.o
OBJS += passes/cmds/delete.o
OBJS += passes/cmds/design.o
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index 7b76f3d4a..c49b8bf5d 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -206,6 +206,7 @@ struct AddPass : public Pass {
extra_args(args, argidx, design);
+ bool selected_anything = false;
for (auto module : design->modules())
{
log_assert(module != nullptr);
@@ -214,11 +215,14 @@ struct AddPass : public Pass {
if (module->get_bool_attribute("\\blackbox"))
continue;
+ selected_anything = true;
if (is_formal_celltype(command))
add_formal(module, command, arg_name, enable_name);
else if (command == "wire")
add_wire(design, module, arg_name, arg_width, arg_flag_input, arg_flag_output, arg_flag_global);
}
+ if (!selected_anything)
+ log_warning("No modules selected, or only blackboxes. Nothing was added.\n");
}
} AddPass;
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 172addcc1..fab23fc1d 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -18,6 +18,7 @@
*/
#include "kernel/yosys.h"
+#include "frontends/verilog/preproc.h"
#include "frontends/ast/ast.h"
YOSYS_NAMESPACE_BEGIN
@@ -346,7 +347,7 @@ struct DesignPass : public Pass {
delete node;
design->verilog_globals.clear();
- design->verilog_defines.clear();
+ design->verilog_defines->clear();
}
if (!load_name.empty() || pop_mode)
diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc
new file mode 100644
index 000000000..7eeefe705
--- /dev/null
+++ b/passes/cmds/exec.cc
@@ -0,0 +1,205 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/log.h"
+#include <cstdio>
+
+#if defined(_WIN32)
+# include <csignal>
+# define WIFEXITED(x) 1
+# define WIFSIGNALED(x) 0
+# define WIFSTOPPED(x) 0
+# define WEXITSTATUS(x) ((x) & 0xff)
+# define WTERMSIG(x) SIGTERM
+# define WSTOPSIG(x) 0
+#else
+# include <sys/wait.h>
+#endif
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct ExecPass : public Pass {
+ ExecPass() : Pass("exec", "execute commands in the operating system shell") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" exec [options] -- [command]\n");
+ log("\n");
+ log("Execute a command in the operating system shell. All supplied arguments are\n");
+ log("concatenated and passed as a command to popen(3). Whitespace is not guaranteed\n");
+ log("to be preserved, even if quoted. stdin and stderr are not connected, while stdout is\n");
+ log("logged unless the \"-q\" option is specified.\n");
+ log("\n");
+ log("\n");
+ log(" -q\n");
+ log(" Suppress stdout and stderr from subprocess\n");
+ log("\n");
+ log(" -expect-return <int>\n");
+ log(" Generate an error if popen() does not return specified value.\n");
+ log(" May only be specified once; the final specified value is controlling\n");
+ log(" if specified multiple times.\n");
+ log("\n");
+ log(" -expect-stdout <regex>\n");
+ log(" Generate an error if the specified regex does not match any line\n");
+ log(" in subprocess's stdout. May be specified multiple times.\n");
+ log("\n");
+ log(" -not-expect-stdout <regex>\n");
+ log(" Generate an error if the specified regex matches any line\n");
+ log(" in subprocess's stdout. May be specified multiple times.\n");
+ log("\n");
+ log("\n");
+ log(" Example: exec -q -expect-return 0 -- echo \"bananapie\" | grep \"nana\"\n");
+ log("\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ std::string cmd = "";
+ char buf[1024] = {};
+ std::string linebuf = "";
+ bool flag_cmd = false;
+ bool flag_quiet = false;
+ bool flag_expect_return = false;
+ int expect_return_value = 0;
+ bool flag_expect_stdout = false;
+ struct expect_stdout_elem {
+ bool matched;
+ bool polarity; //true: this regex must match at least one line
+ //false: this regex must not match any line
+ std::string str;
+ YS_REGEX_TYPE re;
+
+ expect_stdout_elem() : matched(false), polarity(true), str(), re(){};
+ };
+ std::vector<expect_stdout_elem> expect_stdout;
+
+ if(args.size() == 0)
+ log_cmd_error("No command provided.\n");
+
+ for(size_t argidx = 1; argidx < args.size(); ++argidx) {
+ if (flag_cmd) {
+ cmd += args[argidx] + (argidx != (args.size() - 1)? " " : "");
+ } else {
+ if (args[argidx] == "--")
+ flag_cmd = true;
+ else if (args[argidx] == "-q")
+ flag_quiet = true;
+ else if (args[argidx] == "-expect-return") {
+ flag_expect_return = true;
+ ++argidx;
+ if (argidx >= args.size())
+ log_cmd_error("No expected return value specified.\n");
+
+ expect_return_value = atoi(args[argidx].c_str());
+ } else if (args[argidx] == "-expect-stdout") {
+ flag_expect_stdout = true;
+ ++argidx;
+ if (argidx >= args.size())
+ log_cmd_error("No expected regular expression specified.\n");
+
+ try{
+ expect_stdout_elem x;
+ x.str = args[argidx];
+ x.re = YS_REGEX_COMPILE(args[argidx]);
+ expect_stdout.push_back(x);
+ } catch (const YS_REGEX_NS::regex_error& e) {
+ log_cmd_error("Error in regex expression '%s' !\n", args[argidx].c_str());
+ }
+ } else if (args[argidx] == "-not-expect-stdout") {
+ flag_expect_stdout = true;
+ ++argidx;
+ if (argidx >= args.size())
+ log_cmd_error("No expected regular expression specified.\n");
+
+ try{
+ expect_stdout_elem x;
+ x.str = args[argidx];
+ x.re = YS_REGEX_COMPILE(args[argidx]);
+ x.polarity = false;
+ expect_stdout.push_back(x);
+ } catch (const YS_REGEX_NS::regex_error& e) {
+ log_cmd_error("Error in regex expression '%s' !\n", args[argidx].c_str());
+ }
+
+ } else
+ log_cmd_error("Unknown option \"%s\" or \"--\" doesn\'t precede command.", args[argidx].c_str());
+ }
+ }
+
+ log_header(design, "Executing command \"%s\".\n", cmd.c_str());
+ log_push();
+
+ fflush(stdout);
+ bool keep_reading = true;
+ int status = 0;
+ int retval = 0;
+
+#ifndef EMSCRIPTEN
+ FILE *f = popen(cmd.c_str(), "r");
+ if (f == nullptr)
+ log_cmd_error("errno %d after popen() returned NULL.\n", errno);
+ while (keep_reading) {
+ keep_reading = (fgets(buf, sizeof(buf), f) != nullptr);
+ linebuf += buf;
+ memset(buf, 0, sizeof(buf));
+
+ auto pos = linebuf.find('\n');
+ while (pos != std::string::npos) {
+ std::string line = linebuf.substr(0, pos);
+ linebuf.erase(0, pos + 1);
+ if (!flag_quiet)
+ log("%s\n", line.c_str());
+
+ if (flag_expect_stdout)
+ for(auto &x : expect_stdout)
+ if (YS_REGEX_NS::regex_search(line, x.re))
+ x.matched = true;
+
+ pos = linebuf.find('\n');
+ }
+ }
+ status = pclose(f);
+#endif
+
+ if(WIFEXITED(status)) {
+ retval = WEXITSTATUS(status);
+ }
+ else if(WIFSIGNALED(status)) {
+ retval = WTERMSIG(status);
+ }
+ else if(WIFSTOPPED(status)) {
+ retval = WSTOPSIG(status);
+ }
+
+ if (flag_expect_return && retval != expect_return_value)
+ log_cmd_error("Return value %d did not match expected return value %d.\n", retval, expect_return_value);
+
+ if (flag_expect_stdout)
+ for (auto &x : expect_stdout)
+ if (x.polarity ^ x.matched)
+ log_cmd_error("Command stdout did%s have a line matching given regex \"%s\".\n", (x.polarity? " not" : ""), x.str.c_str());
+
+ log_pop();
+ }
+} ExecPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 1657ef818..b64b077e4 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -625,9 +625,13 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se
}
}
-static void select_stmt(RTLIL::Design *design, std::string arg)
+static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_empty_warning = false)
{
std::string arg_mod, arg_memb;
+ std::unordered_map<std::string, bool> arg_mod_found;
+ std::unordered_map<std::string, bool> arg_memb_found;
+ auto isalpha = [](const char &x) { return ((x >= 'a' && x <= 'z') || (x >= 'A' && x <= 'Z')); };
+ bool prefixed = GetSize(arg) >= 2 && isalpha(arg[0]) && arg[1] == ':';
if (arg.size() == 0)
return;
@@ -758,19 +762,21 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
if (!design->selected_active_module.empty()) {
arg_mod = design->selected_active_module;
arg_memb = arg;
+ if (!prefixed) arg_memb_found[arg_memb] = false;
} else
- if (GetSize(arg) >= 2 && arg[0] >= 'a' && arg[0] <= 'z' && arg[1] == ':') {
+ if (prefixed && arg[0] >= 'a' && arg[0] <= 'z') {
arg_mod = "*", arg_memb = arg;
} else {
size_t pos = arg.find('/');
if (pos == std::string::npos) {
- if (arg.find(':') == std::string::npos || arg.compare(0, 1, "A") == 0)
- arg_mod = arg;
- else
- arg_mod = "*", arg_memb = arg;
+ arg_mod = arg;
+ if (!prefixed) arg_mod_found[arg_mod] = false;
} else {
arg_mod = arg.substr(0, pos);
+ if (!prefixed) arg_mod_found[arg_mod] = false;
arg_memb = arg.substr(pos+1);
+ bool arg_memb_prefixed = GetSize(arg_memb) >= 2 && isalpha(arg_memb[0]) && arg_memb[1] == ':';
+ if (!arg_memb_prefixed) arg_memb_found[arg_memb] = false;
}
}
@@ -789,8 +795,14 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
if (!match_attr(mod->attributes, arg_mod.substr(2)))
continue;
} else
+ if (arg_mod.compare(0, 2, "N:") == 0) {
+ if (!match_ids(mod->name, arg_mod.substr(2)))
+ continue;
+ } else
if (!match_ids(mod->name, arg_mod))
continue;
+ else
+ arg_mod_found[arg_mod] = true;
if (arg_memb == "") {
sel.selected_modules.insert(mod->name);
@@ -839,7 +851,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
if (match_ids(it.first, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
} else
- if (arg_memb.compare(0, 2, "c:") ==0) {
+ if (arg_memb.compare(0, 2, "c:") == 0) {
for (auto cell : mod->cells())
if (match_ids(cell->name, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(cell->name);
@@ -873,24 +885,44 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
if (match_attr(cell->parameters, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(cell->name);
} else {
+ std::string orig_arg_memb = arg_memb;
if (arg_memb.compare(0, 2, "n:") == 0)
arg_memb = arg_memb.substr(2);
for (auto wire : mod->wires())
- if (match_ids(wire->name, arg_memb))
+ if (match_ids(wire->name, arg_memb)) {
sel.selected_members[mod->name].insert(wire->name);
+ arg_memb_found[orig_arg_memb] = true;
+ }
for (auto &it : mod->memories)
- if (match_ids(it.first, arg_memb))
+ if (match_ids(it.first, arg_memb)) {
sel.selected_members[mod->name].insert(it.first);
+ arg_memb_found[orig_arg_memb] = true;
+ }
for (auto cell : mod->cells())
- if (match_ids(cell->name, arg_memb))
+ if (match_ids(cell->name, arg_memb)) {
sel.selected_members[mod->name].insert(cell->name);
+ arg_memb_found[orig_arg_memb] = true;
+ }
for (auto &it : mod->processes)
- if (match_ids(it.first, arg_memb))
+ if (match_ids(it.first, arg_memb)) {
sel.selected_members[mod->name].insert(it.first);
+ arg_memb_found[orig_arg_memb] = true;
+ }
}
}
select_filter_active_mod(design, work_stack.back());
+
+ for (auto &it : arg_mod_found) {
+ if (it.second == false && !disable_empty_warning) {
+ log_warning("Selection \"%s\" did not match any module.\n", it.first.c_str());
+ }
+ }
+ for (auto &it : arg_memb_found) {
+ if (it.second == false && !disable_empty_warning) {
+ log_warning("Selection \"%s\" did not match any object.\n", it.first.c_str());
+ }
+ }
}
static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::Selection *sel)
@@ -1074,6 +1106,10 @@ struct SelectPass : public Pass {
log(" all modules with an attribute matching the given pattern\n");
log(" in addition to = also <, <=, >=, and > are supported\n");
log("\n");
+ log(" N:<pattern>\n");
+ log(" all modules with a name matching the given pattern\n");
+ log(" (i.e. 'N:' is optional as it is the default matching rule)\n");
+ log("\n");
log("An <obj_pattern> can be an object name, wildcard expression, or one of\n");
log("the following:\n");
log("\n");
@@ -1276,7 +1312,8 @@ struct SelectPass : public Pass {
}
if (arg.size() > 0 && arg[0] == '-')
log_cmd_error("Unknown option %s.\n", arg.c_str());
- select_stmt(design, arg);
+ bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_count != -1) || (assert_max != -1) || (assert_min != -1);
+ select_stmt(design, arg, disable_empty_warning);
sel_str += " " + arg;
}
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index a85c3bec0..0f7b4d106 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -422,11 +422,7 @@ struct FsmExtractPass : public Pass {
log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
extra_args(args, 1, design);
- CellTypes ct;
- ct.setup_internals();
- ct.setup_internals_mem();
- ct.setup_stdcells();
- ct.setup_stdcells_mem();
+ CellTypes ct(design);
for (auto &mod_it : design->modules_)
{
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index e0bb439f4..148480d55 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -88,25 +88,24 @@ struct BruteForceEquivChecker
mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
{
log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
- for (auto &w : mod1->wires_)
+ for (auto w : mod1->wires())
{
- RTLIL::Wire *wire1 = w.second;
- if (wire1->port_id == 0)
+ if (w->port_id == 0)
continue;
- if (mod2->wires_.count(wire1->name) == 0)
- log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", wire1->name.c_str());
+ if (mod2->wire(w->name) == nullptr)
+ log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", w->name.c_str());
- RTLIL::Wire *wire2 = mod2->wires_.at(wire1->name);
- if (wire1->width != wire2->width || wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output)
- log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", wire1->name.c_str());
+ RTLIL::Wire *w2 = mod2->wire(w->name);
+ if (w->width != w2->width || w->port_input != w2->port_input || w->port_output != w2->port_output)
+ log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", w->name.c_str());
- if (wire1->port_input) {
- mod1_inputs.append(wire1);
- mod2_inputs.append(wire2);
+ if (w->port_input) {
+ mod1_inputs.append(w);
+ mod2_inputs.append(w2);
} else {
- mod1_outputs.append(wire1);
- mod2_outputs.append(wire2);
+ mod1_outputs.append(w);
+ mod2_outputs.append(w2);
}
}
@@ -148,17 +147,17 @@ struct VlogHammerReporter
SatGen satgen(ez.get(), &sigmap);
satgen.model_undef = model_undef;
- for (auto &c : module->cells_)
- if (!satgen.importCell(c.second))
- log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
+ for (auto c : module->cells())
+ if (!satgen.importCell(c))
+ log_error("Failed to import cell %s (type %s) to SAT database.\n", log_id(c->name), log_id(c->type));
ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
- std::vector<int> y_vec = satgen.importDefSigSpec(module->wires_.at("\\y"));
+ std::vector<int> y_vec = satgen.importDefSigSpec(module->wire("\\y"));
std::vector<bool> y_values;
if (model_undef) {
- std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wires_.at("\\y"));
+ std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire("\\y"));
y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end());
}
@@ -253,7 +252,7 @@ struct VlogHammerReporter
std::vector<RTLIL::State> bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width);
for (int i = 0; i < int(inputs.size()); i++) {
- RTLIL::Wire *wire = module->wires_.at(inputs[i]);
+ RTLIL::Wire *wire = module->wire(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
@@ -263,21 +262,21 @@ struct VlogHammerReporter
if (module == modules.front()) {
RTLIL::SigSpec sig(wire);
if (!ce.eval(sig))
- log_error("Can't read back value for port %s!\n", RTLIL::id2cstr(inputs[i]));
+ log_error("Can't read back value for port %s!\n", log_id(inputs[i]));
input_pattern_list += stringf(" %s", sig.as_const().as_string().c_str());
- log("++PAT++ %d %s %s #\n", idx, RTLIL::id2cstr(inputs[i]), sig.as_const().as_string().c_str());
+ log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string().c_str());
}
}
- if (module->wires_.count("\\y") == 0)
- log_error("No output wire (y) found in module %s!\n", RTLIL::id2cstr(module->name));
+ if (module->wire("\\y") == nullptr)
+ log_error("No output wire (y) found in module %s!\n", log_id(module->name));
- RTLIL::SigSpec sig(module->wires_.at("\\y"));
+ RTLIL::SigSpec sig(module->wire("\\y"));
RTLIL::SigSpec undef;
while (!ce.eval(sig, undef)) {
- // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef));
- log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
+ // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", log_id(module->name), log_signal(sig), log_signal(undef));
+ log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), log_id(module->name));
ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
}
@@ -289,7 +288,7 @@ struct VlogHammerReporter
sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
} else if (rtl_sig.size() > 0) {
if (rtl_sig.size() != sig.size())
- log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
+ log_error("Output (y) has a different width in module %s compared to rtl!\n", log_id(module->name));
for (int i = 0; i < GetSize(sig); i++)
if (rtl_sig[i] == RTLIL::State::Sx)
sig[i] = RTLIL::State::Sx;
@@ -307,10 +306,10 @@ struct VlogHammerReporter
{
for (auto name : split(module_list, ",")) {
RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name);
- if (design->modules_.count(esc_name) == 0)
+ if (design->module(esc_name) == nullptr)
log_error("Can't find module %s in current design!\n", name.c_str());
log("Using module %s (%s).\n", esc_name.c_str(), name.c_str());
- modules.push_back(design->modules_.at(esc_name));
+ modules.push_back(design->module(esc_name));
module_names.push_back(name);
}
@@ -319,11 +318,11 @@ struct VlogHammerReporter
int width = -1;
RTLIL::IdString esc_name = RTLIL::escape_id(name);
for (auto mod : modules) {
- if (mod->wires_.count(esc_name) == 0)
- log_error("Can't find input %s in module %s!\n", name.c_str(), RTLIL::id2cstr(mod->name));
- RTLIL::Wire *port = mod->wires_.at(esc_name);
+ if (mod->wire(esc_name) == nullptr)
+ log_error("Can't find input %s in module %s!\n", name.c_str(), log_id(mod->name));
+ RTLIL::Wire *port = mod->wire(esc_name);
if (!port->port_input || port->port_output)
- log_error("Wire %s in module %s is not an input!\n", name.c_str(), RTLIL::id2cstr(mod->name));
+ log_error("Wire %s in module %s is not an input!\n", name.c_str(), log_id(mod->name));
if (width >= 0 && width != port->width)
log_error("Port %s has different sizes in the different modules!\n", name.c_str());
width = port->width;
@@ -415,11 +414,11 @@ struct EvalPass : public Pass {
/* this should only be used for regression testing of ConstEval -- see vloghammer */
std::string mod1_name = RTLIL::escape_id(args[++argidx]);
std::string mod2_name = RTLIL::escape_id(args[++argidx]);
- if (design->modules_.count(mod1_name) == 0)
+ if (design->module(mod1_name) == nullptr)
log_error("Can't find module `%s'!\n", mod1_name.c_str());
- if (design->modules_.count(mod2_name) == 0)
+ if (design->module(mod2_name) == nullptr)
log_error("Can't find module `%s'!\n", mod2_name.c_str());
- BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
+ BruteForceEquivChecker checker(design->module(mod1_name), design->module(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
if (checker.errors > 0)
log_cmd_error("Modules are not equivalent!\n");
log("Verified %s = %s (using brute-force check on %d cases).\n",
@@ -441,13 +440,12 @@ struct EvalPass : public Pass {
extra_args(args, argidx, design);
RTLIL::Module *module = NULL;
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second)) {
- if (module)
- log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
- RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first));
- module = mod_it.second;
- }
+ for (auto mod : design->selected_modules()) {
+ if (module)
+ log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
+ log_id(module->name), log_id(mod->name));
+ module = mod;
+ }
if (module == NULL)
log_cmd_error("Can't perform EVAL on an empty selection!\n");
@@ -468,9 +466,9 @@ struct EvalPass : public Pass {
}
if (shows.size() == 0) {
- for (auto &it : module->wires_)
- if (it.second->port_output)
- shows.push_back(it.second->name.str());
+ for (auto w : module->wires())
+ if (w->port_output)
+ shows.push_back(w->name.str());
}
if (tables.empty())
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index f29631639..54016e528 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -614,29 +614,29 @@ struct FreduceWorker
int bits_full_total = 0;
std::vector<std::set<RTLIL::SigBit>> batches;
- for (auto &it : module->wires_)
- if (it.second->port_input) {
- batches.push_back(sigmap(it.second).to_sigbit_set());
- bits_full_total += it.second->width;
+ for (auto w : module->wires())
+ if (w->port_input) {
+ batches.push_back(sigmap(w).to_sigbit_set());
+ bits_full_total += w->width;
}
- for (auto &it : module->cells_) {
- if (ct.cell_known(it.second->type)) {
+ for (auto cell : module->cells()) {
+ if (ct.cell_known(cell->type)) {
std::set<RTLIL::SigBit> inputs, outputs;
- for (auto &port : it.second->connections()) {
+ for (auto &port : cell->connections()) {
std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
- if (ct.cell_output(it.second->type, port.first))
+ if (ct.cell_output(cell->type, port.first))
outputs.insert(bits.begin(), bits.end());
else
inputs.insert(bits.begin(), bits.end());
}
- std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(it.second, inputs);
+ std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(cell, inputs);
for (auto &bit : outputs)
drivers[bit] = drv;
batches.push_back(outputs);
bits_full_total += outputs.size();
}
- if (inv_mode && it.second->type == "$_NOT_")
- inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y"))));
+ if (inv_mode && cell->type == "$_NOT_")
+ inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\Y"))));
}
int bits_count = 0;
@@ -828,10 +828,8 @@ struct FreducePass : public Pass {
extra_args(args, argidx, design);
int bitcount = 0;
- for (auto &mod_it : design->modules_) {
- RTLIL::Module *module = mod_it.second;
- if (design->selected(module))
- bitcount += FreduceWorker(design, module).run();
+ for (auto module : design->selected_modules()) {
+ bitcount += FreduceWorker(design, module).run();
}
log("Rewired a total of %d signal bits.\n", bitcount);
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 49ef40061..742433935 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -66,50 +66,48 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
RTLIL::IdString gate_name = RTLIL::escape_id(args[argidx++]);
RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]);
- if (design->modules_.count(gold_name) == 0)
+ if (design->module(gold_name) == nullptr)
log_cmd_error("Can't find gold module %s!\n", gold_name.c_str());
- if (design->modules_.count(gate_name) == 0)
+ if (design->module(gate_name) == nullptr)
log_cmd_error("Can't find gate module %s!\n", gate_name.c_str());
- if (design->modules_.count(miter_name) != 0)
+ if (design->module(miter_name) != nullptr)
log_cmd_error("There is already a module %s!\n", miter_name.c_str());
- RTLIL::Module *gold_module = design->modules_.at(gold_name);
- RTLIL::Module *gate_module = design->modules_.at(gate_name);
+ RTLIL::Module *gold_module = design->module(gold_name);
+ RTLIL::Module *gate_module = design->module(gate_name);
- for (auto &it : gold_module->wires_) {
- RTLIL::Wire *w1 = it.second, *w2;
- if (w1->port_id == 0)
+ for (auto gold_wire : gold_module->wires()) {
+ if (gold_wire->port_id == 0)
continue;
- if (gate_module->wires_.count(it.second->name) == 0)
+ RTLIL::Wire *gate_wire = gate_module->wire(gold_wire->name);
+ if (gate_wire == nullptr)
goto match_gold_port_error;
- w2 = gate_module->wires_.at(it.second->name);
- if (w1->port_input != w2->port_input)
+ if (gold_wire->port_input != gate_wire->port_input)
goto match_gold_port_error;
- if (w1->port_output != w2->port_output)
+ if (gold_wire->port_output != gate_wire->port_output)
goto match_gold_port_error;
- if (w1->width != w2->width)
+ if (gold_wire->width != gate_wire->width)
goto match_gold_port_error;
continue;
match_gold_port_error:
- log_cmd_error("No matching port in gate module was found for %s!\n", it.second->name.c_str());
+ log_cmd_error("No matching port in gate module was found for %s!\n", gold_wire->name.c_str());
}
- for (auto &it : gate_module->wires_) {
- RTLIL::Wire *w1 = it.second, *w2;
- if (w1->port_id == 0)
+ for (auto gate_wire : gate_module->wires()) {
+ if (gate_wire->port_id == 0)
continue;
- if (gold_module->wires_.count(it.second->name) == 0)
+ RTLIL::Wire *gold_wire = gold_module->wire(gate_wire->name);
+ if (gold_wire == nullptr)
goto match_gate_port_error;
- w2 = gold_module->wires_.at(it.second->name);
- if (w1->port_input != w2->port_input)
+ if (gate_wire->port_input != gold_wire->port_input)
goto match_gate_port_error;
- if (w1->port_output != w2->port_output)
+ if (gate_wire->port_output != gold_wire->port_output)
goto match_gate_port_error;
- if (w1->width != w2->width)
+ if (gate_wire->width != gold_wire->width)
goto match_gate_port_error;
continue;
match_gate_port_error:
- log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str());
+ log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name.c_str());
}
log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name));
@@ -123,73 +121,71 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
RTLIL::SigSpec all_conditions;
- for (auto &it : gold_module->wires_)
+ for (auto gold_wire : gold_module->wires())
{
- RTLIL::Wire *w1 = it.second;
-
- if (w1->port_input)
+ if (gold_wire->port_input)
{
- RTLIL::Wire *w2 = miter_module->addWire("\\in_" + RTLIL::unescape_id(w1->name), w1->width);
- w2->port_input = true;
+ RTLIL::Wire *w = miter_module->addWire("\\in_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
+ w->port_input = true;
- gold_cell->setPort(w1->name, w2);
- gate_cell->setPort(w1->name, w2);
+ gold_cell->setPort(gold_wire->name, w);
+ gate_cell->setPort(gold_wire->name, w);
}
- if (w1->port_output)
+ if (gold_wire->port_output)
{
- RTLIL::Wire *w2_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(w1->name), w1->width);
- w2_gold->port_output = flag_make_outputs;
+ RTLIL::Wire *w_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
+ w_gold->port_output = flag_make_outputs;
- RTLIL::Wire *w2_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(w1->name), w1->width);
- w2_gate->port_output = flag_make_outputs;
+ RTLIL::Wire *w_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
+ w_gate->port_output = flag_make_outputs;
- gold_cell->setPort(w1->name, w2_gold);
- gate_cell->setPort(w1->name, w2_gate);
+ gold_cell->setPort(gold_wire->name, w_gold);
+ gate_cell->setPort(gold_wire->name, w_gate);
RTLIL::SigSpec this_condition;
if (flag_ignore_gold_x)
{
- RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width);
- for (int i = 0; i < w2_gold->width; i++) {
+ RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w_gold->width);
+ for (int i = 0; i < w_gold->width; i++) {
RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, "$eqx");
eqx_cell->parameters["\\A_WIDTH"] = 1;
eqx_cell->parameters["\\B_WIDTH"] = 1;
eqx_cell->parameters["\\Y_WIDTH"] = 1;
eqx_cell->parameters["\\A_SIGNED"] = 0;
eqx_cell->parameters["\\B_SIGNED"] = 0;
- eqx_cell->setPort("\\A", RTLIL::SigSpec(w2_gold, i));
+ eqx_cell->setPort("\\A", RTLIL::SigSpec(w_gold, i));
eqx_cell->setPort("\\B", RTLIL::State::Sx);
eqx_cell->setPort("\\Y", gold_x.extract(i, 1));
}
- RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width);
- RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width);
+ RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width);
+ RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w_gate->width);
RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, "$or");
- or_gold_cell->parameters["\\A_WIDTH"] = w2_gold->width;
- or_gold_cell->parameters["\\B_WIDTH"] = w2_gold->width;
- or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width;
+ or_gold_cell->parameters["\\A_WIDTH"] = w_gold->width;
+ or_gold_cell->parameters["\\B_WIDTH"] = w_gold->width;
+ or_gold_cell->parameters["\\Y_WIDTH"] = w_gold->width;
or_gold_cell->parameters["\\A_SIGNED"] = 0;
or_gold_cell->parameters["\\B_SIGNED"] = 0;
- or_gold_cell->setPort("\\A", w2_gold);
+ or_gold_cell->setPort("\\A", w_gold);
or_gold_cell->setPort("\\B", gold_x);
or_gold_cell->setPort("\\Y", gold_masked);
RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
- or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width;
- or_gate_cell->parameters["\\B_WIDTH"] = w2_gate->width;
- or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width;
+ or_gate_cell->parameters["\\A_WIDTH"] = w_gate->width;
+ or_gate_cell->parameters["\\B_WIDTH"] = w_gate->width;
+ or_gate_cell->parameters["\\Y_WIDTH"] = w_gate->width;
or_gate_cell->parameters["\\A_SIGNED"] = 0;
or_gate_cell->parameters["\\B_SIGNED"] = 0;
- or_gate_cell->setPort("\\A", w2_gate);
+ or_gate_cell->setPort("\\A", w_gate);
or_gate_cell->setPort("\\B", gold_x);
or_gate_cell->setPort("\\Y", gate_masked);
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
- eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
- eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
+ eq_cell->parameters["\\A_WIDTH"] = w_gold->width;
+ eq_cell->parameters["\\B_WIDTH"] = w_gate->width;
eq_cell->parameters["\\Y_WIDTH"] = 1;
eq_cell->parameters["\\A_SIGNED"] = 0;
eq_cell->parameters["\\B_SIGNED"] = 0;
@@ -201,20 +197,20 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
else
{
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
- eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
- eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
+ eq_cell->parameters["\\A_WIDTH"] = w_gold->width;
+ eq_cell->parameters["\\B_WIDTH"] = w_gate->width;
eq_cell->parameters["\\Y_WIDTH"] = 1;
eq_cell->parameters["\\A_SIGNED"] = 0;
eq_cell->parameters["\\B_SIGNED"] = 0;
- eq_cell->setPort("\\A", w2_gold);
- eq_cell->setPort("\\B", w2_gate);
+ eq_cell->setPort("\\A", w_gold);
+ eq_cell->setPort("\\B", w_gate);
eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
this_condition = eq_cell->getPort("\\Y");
}
if (flag_make_outcmp)
{
- RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(w1->name));
+ RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(gold_wire->name));
w_cmp->port_output = true;
miter_module->connect(RTLIL::SigSig(w_cmp, this_condition));
}
@@ -285,9 +281,9 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
IdString module_name = RTLIL::escape_id(args[argidx++]);
IdString miter_name = argidx < args.size() ? RTLIL::escape_id(args[argidx++]) : "";
- if (design->modules_.count(module_name) == 0)
+ if (design->module(module_name) == nullptr)
log_cmd_error("Can't find module %s!\n", module_name.c_str());
- if (!miter_name.empty() && design->modules_.count(miter_name) != 0)
+ if (!miter_name.empty() && design->module(miter_name) != nullptr)
log_cmd_error("There is already a module %s!\n", miter_name.c_str());
Module *module = design->module(module_name);
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index f63012d1a..8b1862237 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -308,7 +308,9 @@ struct IopadmapPass : public Pass {
{
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str());
- Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(tinoutpad_celltype));
+ Cell *cell = module->addCell(
+ module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)),
+ RTLIL::escape_id(tinoutpad_celltype));
cell->setPort(RTLIL::escape_id(tinoutpad_portname_oe), en_sig);
cell->attributes[ID::keep] = RTLIL::Const(1);
@@ -328,7 +330,9 @@ struct IopadmapPass : public Pass {
} else {
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str());
- Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(toutpad_celltype));
+ Cell *cell = module->addCell(
+ module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)),
+ RTLIL::escape_id(toutpad_celltype));
cell->setPort(RTLIL::escape_id(toutpad_portname_oe), en_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname_i), data_sig);
@@ -406,7 +410,9 @@ struct IopadmapPass : public Pass {
SigBit wire_bit(wire, i);
- RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
+ RTLIL::Cell *cell = module->addCell(
+ module->uniquify(stringf("$iopadmap$%s.%s", log_id(module->name), log_id(wire->name))),
+ RTLIL::escape_id(celltype));
cell->setPort(RTLIL::escape_id(portname_int), wire_bit);
if (!portname_pad.empty())
@@ -420,12 +426,16 @@ struct IopadmapPass : public Pass {
}
else
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
+ RTLIL::Cell *cell = module->addCell(
+ module->uniquify(stringf("$iopadmap$%s.%s", log_id(module->name), log_id(wire->name))),
+ RTLIL::escape_id(celltype));
cell->setPort(RTLIL::escape_id(portname_int), RTLIL::SigSpec(wire));
if (!portname_pad.empty()) {
RTLIL::Wire *new_wire = NULL;
- new_wire = module->addWire(NEW_ID, wire);
+ new_wire = module->addWire(
+ module->uniquify(stringf("$iopadmap$%s", log_id(wire))),
+ wire);
module->swap_names(new_wire, wire);
wire->attributes.clear();
cell->setPort(RTLIL::escape_id(portname_pad), RTLIL::SigSpec(new_wire));
@@ -446,7 +456,9 @@ struct IopadmapPass : public Pass {
for (auto &it : rewrite_bits) {
RTLIL::Wire *wire = it.first;
- RTLIL::Wire *new_wire = module->addWire(NEW_ID, wire);
+ RTLIL::Wire *new_wire = module->addWire(
+ module->uniquify(stringf("$iopadmap$%s", log_id(wire))),
+ wire);
module->swap_names(new_wire, wire);
wire->attributes.clear();
for (int i = 0; i < wire->width; i++)
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 0c57733d4..10001baaa 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -177,10 +177,10 @@ struct TechmapWorker
std::string orig_cell_name;
pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
+ orig_cell_name = cell->name.str();
if (!flatten_mode) {
for (auto &it : tpl->cells_)
if (it.first == ID(_TECHMAP_REPLACE_)) {
- orig_cell_name = cell->name.str();
module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
break;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-17 01:59:58 +0000