diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/wreduce.cc | 2 | ||||
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index f749c8249..1fbc41082 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -497,7 +497,7 @@ struct WreducePass : public Pass { log(" flows that use the 'memory_memx' pass.\n"); log("\n"); log(" -keepdc\n"); - log(" Do not optimize explicit don't-care values on $mux cells.\n"); + log(" Do not optimize explicit don't-care values.\n"); log("\n"); } void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 49ec795d3..4bb4aa047 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -253,6 +253,13 @@ struct Clk2fflogicPass : public Pass { SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge); Const rstval = cell->parameters["\\ARST_VALUE"]; + Wire *past_arst = module->addWire(NEW_ID); + module->addFf(NEW_ID, arst, past_arst); + if (cell->parameters["\\ARST_POLARITY"].as_bool()) + arst = module->LogicOr(NEW_ID, arst, past_arst); + else + arst = module->LogicAnd(NEW_ID, arst, past_arst); + if (cell->parameters["\\ARST_POLARITY"].as_bool()) module->addMux(NEW_ID, qval, rstval, arst, sig_q); else |