diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/select.cc | 4 | ||||
| -rw-r--r-- | passes/pmgen/Makefile.inc | 2 | ||||
| -rw-r--r-- | passes/techmap/abc9.cc | 26 |
3 files changed, 13 insertions, 19 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 59d10a1b8..0f1f05ccb 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -664,7 +664,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } else if (arg == "%D") { if (work_stack.size() < 2) - log_cmd_error("Must have at least two elements on the stack for operator %%d.\n"); + log_cmd_error("Must have at least two elements on the stack for operator %%D.\n"); select_op_diff(design, work_stack[work_stack.size()-1], work_stack[work_stack.size()-2]); work_stack[work_stack.size()-2] = work_stack[work_stack.size()-1]; work_stack.pop_back(); @@ -693,7 +693,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } else if (arg == "%C") { if (work_stack.size() < 1) - log_cmd_error("Must have at least one element on the stack for operator %%M.\n"); + log_cmd_error("Must have at least one element on the stack for operator %%C.\n"); select_op_module_to_cells(design, work_stack[work_stack.size()-1]); } else if (arg == "%c") { diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index e73a7b1c9..4989c582a 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -4,7 +4,7 @@ # -------------------------------------- OBJS += passes/pmgen/test_pmgen.o -passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h +passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h $(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h)) # -------------------------------------- diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 84cb2c04f..6fdf987f0 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -694,30 +694,27 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri int in_wires = 0, out_wires = 0; // Stitch in mapped_mod's inputs/outputs into module - for (auto &it : mapped_mod->wires_) { - RTLIL::Wire *w = it.second; - if (!w->port_input && !w->port_output) - continue; - RTLIL::Wire *wire = module->wire(w->name); + for (auto port : mapped_mod->ports) { + RTLIL::Wire *w = mapped_mod->wire(port); + RTLIL::Wire *wire = module->wire(port); log_assert(wire); - RTLIL::Wire *remap_wire = module->wire(remap_name(w->name)); + RTLIL::Wire *remap_wire = module->wire(remap_name(port)); RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire)); - log_assert(w->port_input || w->port_output); RTLIL::SigSig conn; - if (w->port_input) { - conn.first = remap_wire; - conn.second = signal; - in_wires++; - module->connect(conn); - } if (w->port_output) { conn.first = signal; conn.second = remap_wire; out_wires++; module->connect(conn); } + else if (w->port_input) { + conn.first = remap_wire; + conn.second = signal; + in_wires++; + module->connect(conn); + } } for (auto &it : bit_users) @@ -1300,9 +1297,6 @@ struct Abc9Pass : public Pass { assign_map.clear(); - // The "clean" pass also contains a design->check() call - Pass::call(design, "clean"); - log_pop(); } } Abc9Pass; |