diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/select.cc | 3 | ||||
| -rw-r--r-- | passes/cmds/stat.cc | 9 | ||||
| -rw-r--r-- | passes/fsm/fsmdata.h | 4 | ||||
| -rw-r--r-- | passes/opt/wreduce.cc | 10 | ||||
| -rw-r--r-- | passes/sat/fmcombine.cc | 3 |
5 files changed, 26 insertions, 3 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index d609c8d0f..b112b145c 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -1456,7 +1456,10 @@ struct SelectPass : public Pass { } } if (count_mode) + { + design->scratchpad_set_int("select.count", total_count); log("%d objects.\n", total_count); + } if (f != nullptr) fclose(f); #undef LOG_OBJECT diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index fffdda48e..c858c8631 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -381,6 +381,15 @@ struct StatPass : public Pass { log("\n"); data.log_data(top_mod->name, true); + design->scratchpad_set_int("stat.num_wires", data.num_wires); + design->scratchpad_set_int("stat.num_wire_bits", data.num_wire_bits); + design->scratchpad_set_int("stat.num_pub_wires", data.num_pub_wires); + design->scratchpad_set_int("stat.num_pub_wire_bits", data.num_pub_wire_bits); + design->scratchpad_set_int("stat.num_memories", data.num_memories); + design->scratchpad_set_int("stat.num_memory_bits", data.num_memory_bits); + design->scratchpad_set_int("stat.num_processes", data.num_processes); + design->scratchpad_set_int("stat.num_cells", data.num_cells); + design->scratchpad_set_int("stat.area", data.area); } log("\n"); diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 4ba3b4e4f..97371efab 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -91,8 +91,8 @@ struct FsmData if (reset_state < 0 || reset_state >= state_num) reset_state = -1; - RTLIL::Const state_table = cell->parameters[ID::STATE_TABLE]; - RTLIL::Const trans_table = cell->parameters[ID::TRANS_TABLE]; + const RTLIL::Const &state_table = cell->parameters[ID::STATE_TABLE]; + const RTLIL::Const &trans_table = cell->parameters[ID::TRANS_TABLE]; for (int i = 0; i < state_num; i++) { RTLIL::Const state_code; diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index aaad28ef0..08ab6de6f 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -30,6 +30,7 @@ struct WreduceConfig { pool<IdString> supported_cell_types; bool keepdc = false; + bool mux_undef = false; WreduceConfig() { @@ -83,7 +84,7 @@ struct WreduceWorker SigBit ref = sig_a[i]; for (int k = 0; k < GetSize(sig_s); k++) { - if ((config->keepdc || (ref != State::Sx && sig_b[k*GetSize(sig_a) + i] != State::Sx)) && ref != sig_b[k*GetSize(sig_a) + i]) + if ((config->keepdc || !config->mux_undef || (ref != State::Sx && sig_b[k*GetSize(sig_a) + i] != State::Sx)) && ref != sig_b[k*GetSize(sig_a) + i]) goto no_match_ab; if (sig_b[k*GetSize(sig_a) + i] != State::Sx) ref = sig_b[k*GetSize(sig_a) + i]; @@ -479,6 +480,9 @@ struct WreducePass : public Pass { log(" Do not change the width of memory address ports. Use this options in\n"); log(" flows that use the 'memory_memx' pass.\n"); log("\n"); + log(" -mux_undef\n"); + log(" remove 'undef' inputs from $mux, $pmux and $_MUX_ cells\n"); + log("\n"); log(" -keepdc\n"); log(" Do not optimize explicit don't-care values.\n"); log("\n"); @@ -500,6 +504,10 @@ struct WreducePass : public Pass { config.keepdc = true; continue; } + if (args[argidx] == "-mux_undef") { + config.mux_undef = true; + continue; + } break; } extra_args(args, argidx, design); diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index e15bdf6a8..220cf5c52 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -64,6 +64,9 @@ struct FmcombineWorker c->parameters = cell->parameters; c->attributes = cell->attributes; + if (cell->is_mem_cell()) + c->parameters[ID::MEMID] = cell->parameters[ID::MEMID].decode_string() + suffix; + for (auto &conn : cell->connections()) c->setPort(conn.first, import_sig(conn.second, suffix)); |