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-rw-r--r--passes/cmds/Makefile.inc4
-rw-r--r--passes/cmds/cover.cc4
-rw-r--r--passes/cmds/show.cc12
-rw-r--r--passes/opt/opt_expr.cc52
-rw-r--r--passes/sat/Makefile.inc3
-rw-r--r--passes/techmap/Makefile.inc2
-rw-r--r--passes/techmap/abc.cc11
-rw-r--r--passes/techmap/abc9_exe.cc4
-rw-r--r--passes/techmap/abc9_ops.cc8
9 files changed, 74 insertions, 26 deletions
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 60f20fa6d..a88980eaf 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -1,5 +1,7 @@
+ifeq ($(DISABLE_SPAWN),0)
OBJS += passes/cmds/exec.o
+endif
OBJS += passes/cmds/add.o
OBJS += passes/cmds/delete.o
OBJS += passes/cmds/design.o
@@ -32,6 +34,8 @@ OBJS += passes/cmds/chformal.o
OBJS += passes/cmds/chtype.o
OBJS += passes/cmds/blackbox.o
OBJS += passes/cmds/ltp.o
+ifeq ($(DISABLE_SPAWN),0)
OBJS += passes/cmds/bugpoint.o
+endif
OBJS += passes/cmds/scratchpad.o
OBJS += passes/cmds/logger.o
diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc
index 628ac4c5e..89d27c9aa 100644
--- a/passes/cmds/cover.cc
+++ b/passes/cmds/cover.cc
@@ -101,8 +101,8 @@ struct CoverPass : public Pass {
const std::string &filename = args[++argidx];
FILE *f = nullptr;
if (args[argidx-1] == "-d") {
- #ifdef _WIN32
- log_cmd_error("The 'cover -d' option is not supported on win32.\n");
+ #if defined(_WIN32) || defined(__wasm)
+ log_cmd_error("The 'cover -d' option is not supported on this platform.\n");
#else
char filename_buffer[4096];
snprintf(filename_buffer, 4096, "%s/yosys_cover_%d_XXXXXX.txt", filename.c_str(), getpid());
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 155ed0fcd..fa922454a 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -682,7 +682,7 @@ struct ShowPass : public Pass {
std::vector<std::pair<std::string, RTLIL::Selection>> color_selections;
std::vector<std::pair<std::string, RTLIL::Selection>> label_selections;
-#if defined(EMSCRIPTEN) || defined(_WIN32)
+#if defined(_WIN32) || defined(YOSYS_DISABLE_SPAWN)
std::string format = "dot";
std::string prefix = "show";
#else
@@ -849,10 +849,15 @@ struct ShowPass : public Pass {
std::string cmd = stringf(DOT_CMD, format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str());
#undef DOT_CMD
log("Exec: %s\n", cmd.c_str());
- if (run_command(cmd) != 0)
- log_cmd_error("Shell command failed!\n");
+ #if !defined(YOSYS_DISABLE_SPAWN)
+ if (run_command(cmd) != 0)
+ log_cmd_error("Shell command failed!\n");
+ #endif
}
+ #if defined(YOSYS_DISABLE_SPAWN)
+ log_assert(viewer_exe.empty() && !format.empty());
+ #else
if (!viewer_exe.empty()) {
#ifdef _WIN32
// system()/cmd.exe does not understand single quotes nor
@@ -876,6 +881,7 @@ struct ShowPass : public Pass {
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
}
+ #endif
if (flag_pause) {
#ifdef YOSYS_ENABLE_READLINE
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 2b35ace5e..0f5bff680 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -682,25 +682,37 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
bool sub = cell->type == ID($sub);
+ int minsz = GetSize(sig_y);
+ minsz = std::min(minsz, GetSize(sig_a));
+ minsz = std::min(minsz, GetSize(sig_b));
+
int i;
- for (i = 0; i < GetSize(sig_y); i++) {
- RTLIL::SigBit b = sig_b.at(i, State::Sx);
- RTLIL::SigBit a = sig_a.at(i, State::Sx);
- if (b == State::S0 && a != State::Sx)
+ for (i = 0; i < minsz; i++) {
+ RTLIL::SigBit b = sig_b[i];
+ RTLIL::SigBit a = sig_a[i];
+ if (b == State::S0)
module->connect(sig_y[i], a);
else if (sub && b == State::S1 && a == State::S1)
module->connect(sig_y[i], State::S0);
- else if (!sub && a == State::S0 && b != State::Sx)
+ else if (!sub && a == State::S0)
module->connect(sig_y[i], b);
else
break;
}
if (i > 0) {
cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
- cell->setPort(ID::A, sig_a.extract_end(i));
- cell->setPort(ID::B, sig_b.extract_end(i));
+ log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module));
+ SigSpec new_a = sig_a.extract_end(i);
+ SigSpec new_b = sig_b.extract_end(i);
+ if (new_a.empty() && is_signed)
+ new_a = sig_a[i-1];
+ if (new_b.empty() && is_signed)
+ new_b = sig_b[i-1];
+ cell->setPort(ID::A, new_a);
+ cell->setPort(ID::B, new_b);
cell->setPort(ID::Y, sig_y.extract_end(i));
cell->fixup_parameters();
did_something = true;
@@ -716,6 +728,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec sig_x = cell->getPort(ID::X);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_co = cell->getPort(ID::CO);
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
if (sig_bi != State::S0 && sig_bi != State::S1)
goto skip_fine_alu;
@@ -725,16 +738,20 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
bool bi = sig_bi == State::S1;
bool ci = sig_ci == State::S1;
+ int minsz = GetSize(sig_y);
+ minsz = std::min(minsz, GetSize(sig_a));
+ minsz = std::min(minsz, GetSize(sig_b));
+
int i;
- for (i = 0; i < GetSize(sig_y); i++) {
- RTLIL::SigBit b = sig_b.at(i, State::Sx);
- RTLIL::SigBit a = sig_a.at(i, State::Sx);
- if (b == ((bi ^ ci) ? State::S1 : State::S0) && a != State::Sx) {
+ for (i = 0; i < minsz; i++) {
+ RTLIL::SigBit b = sig_b[i];
+ RTLIL::SigBit a = sig_a[i];
+ if (b == ((bi ^ ci) ? State::S1 : State::S0)) {
module->connect(sig_y[i], a);
module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
- else if (a == (ci ? State::S1 : State::S0) && b != State::Sx) {
+ else if (a == (ci ? State::S1 : State::S0)) {
module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
@@ -744,8 +761,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
if (i > 0) {
cover("opt.opt_expr.fine.$alu");
- cell->setPort(ID::A, sig_a.extract_end(i));
- cell->setPort(ID::B, sig_b.extract_end(i));
+ log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module));
+ SigSpec new_a = sig_a.extract_end(i);
+ SigSpec new_b = sig_b.extract_end(i);
+ if (new_a.empty() && is_signed)
+ new_a = sig_a[i-1];
+ if (new_b.empty() && is_signed)
+ new_b = sig_b[i-1];
+ cell->setPort(ID::A, new_a);
+ cell->setPort(ID::B, new_b);
cell->setPort(ID::X, sig_x.extract_end(i));
cell->setPort(ID::Y, sig_y.extract_end(i));
cell->setPort(ID::CO, sig_co.extract_end(i));
diff --git a/passes/sat/Makefile.inc b/passes/sat/Makefile.inc
index a928c57de..7118c1563 100644
--- a/passes/sat/Makefile.inc
+++ b/passes/sat/Makefile.inc
@@ -13,5 +13,6 @@ OBJS += passes/sat/fmcombine.o
OBJS += passes/sat/mutate.o
OBJS += passes/sat/cutpoint.o
OBJS += passes/sat/fminit.o
+ifeq ($(DISABLE_SPAWN),0)
OBJS += passes/sat/qbfsat.o
-
+endif
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 766b954df..1802ba0de 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -57,7 +57,7 @@ passes/techmap/techmap.inc: techlibs/common/techmap.v
passes/techmap/techmap.o: passes/techmap/techmap.inc
-ifneq ($(CONFIG),emcc)
+ifeq ($(DISABLE_SPAWN),0)
TARGETS += $(PROGRAM_PREFIX)yosys-filterlib$(EXE)
EXTRA_OBJS += passes/techmap/filterlib.o
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index aff0baa44..fae8b2426 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -771,7 +771,10 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
if (abc_script[i] == ';' && abc_script[i+1] == ' ')
abc_script[i+1] = '\n';
- FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
+ std::string buffer = stringf("%s/abc.script", tempdir_name.c_str());
+ FILE *f = fopen(buffer.c_str(), "wt");
+ if (f == nullptr)
+ log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
fprintf(f, "%s\n", abc_script.c_str());
fclose(f);
@@ -807,7 +810,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
handle_loops();
- std::string buffer = stringf("%s/input.blif", tempdir_name.c_str());
+ buffer = stringf("%s/input.blif", tempdir_name.c_str());
f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
@@ -1541,11 +1544,15 @@ struct AbcPass : public Pass {
size_t argidx, g_argidx;
bool g_arg_from_cmd = false;
+#if defined(__wasm)
+ const char *pwd = ".";
+#else
char pwd [PATH_MAX];
if (!getcwd(pwd, sizeof(pwd))) {
log_cmd_error("getcwd failed: %s\n", strerror(errno));
log_abort();
}
+#endif
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
if (arg == "-exe" && argidx+1 < args.size()) {
diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc
index bad91a224..0bf547921 100644
--- a/passes/techmap/abc9_exe.cc
+++ b/passes/techmap/abc9_exe.cc
@@ -420,11 +420,15 @@ struct Abc9ExePass : public Pass {
}
size_t argidx;
+#if defined(__wasm)
+ const char *pwd = ".";
+#else
char pwd [PATH_MAX];
if (!getcwd(pwd, sizeof(pwd))) {
log_cmd_error("getcwd failed: %s\n", strerror(errno));
log_abort();
}
+#endif
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
if (arg == "-exe" && argidx+1 < args.size()) {
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 78c902866..1345188a4 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -741,8 +741,10 @@ void reintegrate(RTLIL::Module *module)
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
- for (auto w : mapped_mod->wires())
- module->addWire(remap_name(w->name), GetSize(w));
+ for (auto w : mapped_mod->wires()) {
+ auto nw = module->addWire(remap_name(w->name), GetSize(w));
+ nw->start_offset = w->start_offset;
+ }
dict<IdString,std::vector<IdString>> box_ports;
@@ -989,7 +991,7 @@ void reintegrate(RTLIL::Module *module)
wire->attributes.erase(ID::abc9_scc);
RTLIL::Wire *remap_wire = module->wire(remap_name(port));
- RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
+ RTLIL::SigSpec signal(wire, remap_wire->start_offset-wire->start_offset, GetSize(remap_wire));
log_assert(GetSize(signal) >= GetSize(remap_wire));
RTLIL::SigSig conn;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 15:18:59 +0000