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-rw-r--r--passes/cmds/Makefile.inc1
-rw-r--r--passes/cmds/portlist.cc93
-rw-r--r--passes/cmds/show.cc8
-rw-r--r--passes/techmap/techmap.cc30
4 files changed, 119 insertions, 13 deletions
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index c8067a8be..cf9663d1d 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -25,6 +25,7 @@ OBJS += passes/cmds/plugin.o
OBJS += passes/cmds/check.o
OBJS += passes/cmds/qwp.o
OBJS += passes/cmds/edgetypes.o
+OBJS += passes/cmds/portlist.o
OBJS += passes/cmds/chformal.o
OBJS += passes/cmds/chtype.o
OBJS += passes/cmds/blackbox.o
diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc
new file mode 100644
index 000000000..38c4a8597
--- /dev/null
+++ b/passes/cmds/portlist.cc
@@ -0,0 +1,93 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct PortlistPass : public Pass {
+ PortlistPass() : Pass("portlist", "list (top-level) ports") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" portlist [options] [selection]\n");
+ log("\n");
+ log("This command lists all module ports found in the selected modules.\n");
+ log("\n");
+ log("If no selection is provided then it lists the ports on the top module.\n");
+ log("\n");
+ log(" -m\n");
+ log(" print verilog blackbox module definitions instead of port lists\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ bool m_mode = false;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ if (args[argidx] == "-m") {
+ m_mode = true;
+ continue;
+ }
+ break;
+ }
+
+ bool first_module = true;
+
+ auto handle_module = [&](RTLIL::Module *module) {
+ vector<string> ports;
+ if (first_module)
+ first_module = false;
+ else
+ log("\n");
+ for (auto port : module->ports) {
+ auto *w = module->wire(port);
+ ports.push_back(stringf("%s [%d:%d] %s", w->port_input ? w->port_output ? "inout" : "input" : "output",
+ w->upto ? w->start_offset : w->start_offset + w->width - 1,
+ w->upto ? w->start_offset + w->width - 1 : w->start_offset,
+ log_id(w)));
+ }
+ log("module %s%s\n", log_id(module), m_mode ? " (" : "");
+ for (int i = 0; i < GetSize(ports); i++)
+ log("%s%s\n", ports[i].c_str(), m_mode && i+1 < GetSize(ports) ? "," : "");
+ if (m_mode)
+ log(");\nendmodule\n");
+ };
+
+ if (argidx == args.size())
+ {
+ auto *top = design->top_module();
+ if (top == nullptr)
+ log_cmd_error("Can't find top module in current design!\n");
+ handle_module(top);
+ }
+ else
+ {
+ extra_args(args, argidx, design);
+ for (auto module : design->selected_modules())
+ handle_module(module);
+ }
+ }
+} PortlistPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 2e9fc72af..a3e969ef1 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -26,6 +26,10 @@
# include <dirent.h>
#endif
+#ifdef __APPLE__
+# include <unistd.h>
+#endif
+
#ifdef YOSYS_ENABLE_READLINE
# include <readline/readline.h>
#endif
@@ -866,7 +870,11 @@ struct ShowPass : public Pass {
log_cmd_error("Shell command failed!\n");
} else
if (format.empty()) {
+ #ifdef __APPLE__
+ std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' &", getuid(), dot_file.c_str(), dot_file.c_str());
+ #else
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid'; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' &", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str());
+ #endif
log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 1d0362ad6..08a1af2d5 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -935,19 +935,6 @@ struct TechmapWorker
for (auto &it2 : it.second)
if (!it2.value.is_fully_const())
log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
- if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_" && techmap_do_cache[tpl]) {
- for (auto &it2 : it.second) {
- auto val = it2.value.as_const();
- auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1));
- auto it = cell->connections().find(wirename);
- if (it != cell->connections().end()) {
- auto sig = sigmap(it->second);
- for (int i = 0; i < sig.size(); i++)
- if (val[i] == State::S1)
- remove_init_bits.insert(sig[i]);
- }
- }
- }
techmap_wire_names.erase(it.first);
}
@@ -973,6 +960,23 @@ struct TechmapWorker
mkdebug.off();
}
+ TechmapWires twd = techmap_find_special_wires(tpl);
+ for (auto &it : twd) {
+ if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_") {
+ for (auto &it2 : it.second) {
+ auto val = it2.value.as_const();
+ auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1));
+ auto it = cell->connections().find(wirename);
+ if (it != cell->connections().end()) {
+ auto sig = sigmap(it->second);
+ for (int i = 0; i < sig.size(); i++)
+ if (val[i] == State::S1)
+ remove_init_bits.insert(sig[i]);
+ }
+ }
+ }
+ }
+
if (extern_mode && !in_recursion)
{
std::string m_name = stringf("$extern:%s", log_id(tpl));
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 20:52:07 +0000