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-rw-r--r--passes/cmds/sta.cc5
-rw-r--r--passes/fsm/fsmdata.h4
-rw-r--r--passes/opt/opt_ffinv.cc4
-rw-r--r--passes/opt/wreduce.cc10
-rw-r--r--passes/techmap/iopadmap.cc28
5 files changed, 40 insertions, 11 deletions
diff --git a/passes/cmds/sta.cc b/passes/cmds/sta.cc
index 13e1ee13c..4ad0e96be 100644
--- a/passes/cmds/sta.cc
+++ b/passes/cmds/sta.cc
@@ -58,11 +58,14 @@ struct StaWorker
{
TimingInfo timing;
+ pool<IdString> unrecognised_cells;
+
for (auto cell : module->cells())
{
Module *inst_module = design->module(cell->type);
if (!inst_module) {
- log_warning("Cell type '%s' not recognised! Ignoring.\n", log_id(cell->type));
+ if (unrecognised_cells.insert(cell->type).second)
+ log_warning("Cell type '%s' not recognised! Ignoring.\n", log_id(cell->type));
continue;
}
diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h
index 4ba3b4e4f..97371efab 100644
--- a/passes/fsm/fsmdata.h
+++ b/passes/fsm/fsmdata.h
@@ -91,8 +91,8 @@ struct FsmData
if (reset_state < 0 || reset_state >= state_num)
reset_state = -1;
- RTLIL::Const state_table = cell->parameters[ID::STATE_TABLE];
- RTLIL::Const trans_table = cell->parameters[ID::TRANS_TABLE];
+ const RTLIL::Const &state_table = cell->parameters[ID::STATE_TABLE];
+ const RTLIL::Const &trans_table = cell->parameters[ID::TRANS_TABLE];
for (int i = 0; i < state_num; i++) {
RTLIL::Const state_code;
diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc
index fd76dd2be..fe5b59fa5 100644
--- a/passes/opt/opt_ffinv.cc
+++ b/passes/opt/opt_ffinv.cc
@@ -72,6 +72,8 @@ struct OptFfInvWorker
for (auto &port: q_ports) {
if (port.cell == ff.cell && port.port == ID::Q)
continue;
+ if (port.cell == d_inv)
+ return false;
if (port.port != ID::A)
return false;
if (!port.cell->type.in(ID($not), ID($_NOT_), ID($lut)))
@@ -148,6 +150,8 @@ struct OptFfInvWorker
for (auto &port: q_ports) {
if (port.cell == ff.cell && port.port == ID::Q)
continue;
+ if (port.cell == d_lut)
+ return false;
if (port.port != ID::A)
return false;
if (port.cell->type.in(ID($not), ID($_NOT_))) {
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index aaad28ef0..08ab6de6f 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -30,6 +30,7 @@ struct WreduceConfig
{
pool<IdString> supported_cell_types;
bool keepdc = false;
+ bool mux_undef = false;
WreduceConfig()
{
@@ -83,7 +84,7 @@ struct WreduceWorker
SigBit ref = sig_a[i];
for (int k = 0; k < GetSize(sig_s); k++) {
- if ((config->keepdc || (ref != State::Sx && sig_b[k*GetSize(sig_a) + i] != State::Sx)) && ref != sig_b[k*GetSize(sig_a) + i])
+ if ((config->keepdc || !config->mux_undef || (ref != State::Sx && sig_b[k*GetSize(sig_a) + i] != State::Sx)) && ref != sig_b[k*GetSize(sig_a) + i])
goto no_match_ab;
if (sig_b[k*GetSize(sig_a) + i] != State::Sx)
ref = sig_b[k*GetSize(sig_a) + i];
@@ -479,6 +480,9 @@ struct WreducePass : public Pass {
log(" Do not change the width of memory address ports. Use this options in\n");
log(" flows that use the 'memory_memx' pass.\n");
log("\n");
+ log(" -mux_undef\n");
+ log(" remove 'undef' inputs from $mux, $pmux and $_MUX_ cells\n");
+ log("\n");
log(" -keepdc\n");
log(" Do not optimize explicit don't-care values.\n");
log("\n");
@@ -500,6 +504,10 @@ struct WreducePass : public Pass {
config.keepdc = true;
continue;
}
+ if (args[argidx] == "-mux_undef") {
+ config.mux_undef = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 437ad5156..322eb7779 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -240,13 +240,13 @@ struct IopadmapPass : public Pass {
for (auto module : design->selected_modules())
{
dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits;
- pool<SigSig> remove_conns;
+ dict<SigSig, pool<int>> remove_conns;
if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
{
dict<SigBit, Cell *> tbuf_bits;
pool<SigBit> driven_bits;
- dict<SigBit, SigSig> z_conns;
+ dict<SigBit, std::pair<SigSig, int>> z_conns;
// Gather tristate buffers and always-on drivers.
for (auto cell : module->cells())
@@ -266,7 +266,7 @@ struct IopadmapPass : public Pass {
SigBit dstbit = conn.first[i];
SigBit srcbit = conn.second[i];
if (!srcbit.wire && srcbit.data == State::Sz) {
- z_conns[dstbit] = conn;
+ z_conns[dstbit] = {conn, i};
continue;
}
driven_bits.insert(dstbit);
@@ -317,8 +317,9 @@ struct IopadmapPass : public Pass {
// enable.
en_sig = SigBit(State::S0);
data_sig = SigBit(State::Sx);
- if (z_conns.count(wire_bit))
- remove_conns.insert(z_conns[wire_bit]);
+ auto it = z_conns.find(wire_bit);
+ if (it != z_conns.end())
+ remove_conns[it->second.first].insert(it->second.second);
}
if (wire->port_input)
@@ -477,9 +478,22 @@ struct IopadmapPass : public Pass {
if (!remove_conns.empty()) {
std::vector<SigSig> new_conns;
- for (auto &conn : module->connections())
- if (!remove_conns.count(conn))
+ for (auto &conn : module->connections()) {
+ auto it = remove_conns.find(conn);
+ if (it == remove_conns.end()) {
new_conns.push_back(conn);
+ } else {
+ SigSpec lhs, rhs;
+ for (int i = 0; i < GetSize(conn.first); i++) {
+ if (!it->second.count(i)) {
+ lhs.append(conn.first[i]);
+ rhs.append(conn.second[i]);
+ }
+ }
+ new_conns.push_back(SigSig(lhs, rhs));
+
+ }
+ }
module->new_connections(new_conns);
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 16:47:28 +0000