diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_expr.cc | 8 | ||||
| -rw-r--r-- | passes/opt/opt_merge.cc | 4 | ||||
| -rw-r--r-- | passes/proc/proc_dlatch.cc | 33 | ||||
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 108 | ||||
| -rw-r--r-- | passes/techmap/abc9.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/clkbufmap.cc | 58 | ||||
| -rw-r--r-- | passes/techmap/dfflegalize.cc | 24 | ||||
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 289 | ||||
| -rw-r--r-- | passes/techmap/extractinv.cc | 2 |
9 files changed, 234 insertions, 294 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 1051a59f2..649ad83a6 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1596,6 +1596,14 @@ skip_identity: log_debug("Removing low %d A and %d B bits from cell `%s' in module `%s'.\n", a_zeros, b_zeros, cell->name.c_str(), module->name.c_str()); + if (y_zeros >= GetSize(sig_y)) { + module->connect(sig_y, RTLIL::SigSpec(0, GetSize(sig_y))); + module->remove(cell); + + did_something = true; + goto next_cell; + } + if (a_zeros) { cell->setPort(ID::A, sig_a.extract_end(a_zeros)); cell->parameters[ID::A_WIDTH] = GetSize(sig_a) - a_zeros; diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index f03faa9cf..9086943dc 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -173,9 +173,7 @@ struct OptMergeWorker for (const auto &it : cell1->connections_) { if (cell1->output(it.first)) { - if (it.first == ID::Q && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || - cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") || - cell1->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) { + if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell1->type)) { // For the 'Q' output of state elements, // use the (* init *) attribute value auto &sig1 = conn1[it.first]; diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index e7c8a80dd..3ed158f37 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -37,6 +37,7 @@ struct proc_dlatch_db_t dict<Cell*, vector<SigBit>> mux_srcbits; dict<SigBit, pair<Cell*, int>> mux_drivers; dict<SigBit, int> sigusers; + dict<SigBit, std::pair<State,SigBit>> initbits; proc_dlatch_db_t(Module *module) : module(module), sigmap(module) { @@ -69,9 +70,34 @@ struct proc_dlatch_db_t } for (auto wire : module->wires()) + { if (wire->port_input) for (auto bit : sigmap(wire)) sigusers[bit]++; + if (wire->attributes.count(ID::init)) { + SigSpec wirebits = sigmap(wire); + Const initval = wire->attributes.at(ID::init); + + for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) + { + SigBit bit = wirebits[i]; + State val = initval[i]; + + if (val != State::S0 && val != State::S1 && bit.wire != nullptr) + continue; + + if (initbits.count(bit)) { + if (initbits.at(bit).first != val) + log_error("Conflicting init values for signal %s (%s = %s != %s).\n", + log_signal(bit), log_signal(SigBit(wire, i)), + log_signal(val), log_signal(initbits.at(bit).first)); + continue; + } + + initbits[bit] = std::make_pair(val,SigBit(wire,i)); + } + } + } } bool quickcheck(const SigSpec &haystack, const SigSpec &needle) @@ -393,6 +419,13 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) else log("No latch inferred for signal `%s.%s' from process `%s.%s'.\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); + for (auto &bit : lhs) { + auto it = db.initbits.find(bit); + if (it != db.initbits.end()) { + log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(it->second.first), db.module->name.c_str(), log_signal(bit), db.module->name.c_str(), proc->name.c_str()); + it->second.second.wire->attributes.at(ID::init)[it->second.second.offset] = State::Sx; + } + } db.module->connect(lhs, rhs); offset += chunk.width; } diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index e5c5d0486..cc24db6d4 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -36,6 +36,30 @@ struct Clk2fflogicPass : public Pass { log("multiple clocks.\n"); log("\n"); } + SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity) { + Wire *past_sig = module->addWire(NEW_ID, GetSize(sig)); + module->addFf(NEW_ID, sig, past_sig); + if (polarity) + sig = module->Or(NEW_ID, sig, past_sig); + else + sig = module->And(NEW_ID, sig, past_sig); + if (polarity) + return sig; + else + return module->Not(NEW_ID, sig); + } + SigSpec wrap_async_control_gate(Module *module, SigSpec sig, bool polarity) { + Wire *past_sig = module->addWire(NEW_ID); + module->addFfGate(NEW_ID, sig, past_sig); + if (polarity) + sig = module->OrGate(NEW_ID, sig, past_sig); + else + sig = module->AndGate(NEW_ID, sig, past_sig); + if (polarity) + return sig; + else + return module->NotGate(NEW_ID, sig); + } void execute(std::vector<std::string> args, RTLIL::Design *design) override { // bool flag_noinit = false; @@ -153,7 +177,7 @@ struct Clk2fflogicPass : public Pass { cell->setPort(ID::WR_DATA, wr_data_port); } - if (cell->type.in(ID($dlatch), ID($dlatchsr))) + if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) { bool enpol = cell->parameters[ID::EN_POLARITY].as_bool(); @@ -165,32 +189,32 @@ struct Clk2fflogicPass : public Pass { log_id(module), log_id(cell), log_id(cell->type), log_signal(sig_en), log_signal(sig_d), log_signal(sig_q)); + sig_en = wrap_async_control(module, sig_en, enpol); + Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q)); module->addFf(NEW_ID, sig_q, past_q); if (cell->type == ID($dlatch)) { - if (enpol) - module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q); - else - module->addMux(NEW_ID, sig_d, past_q, sig_en, sig_q); + module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q); + } + else if (cell->type == ID($adlatch)) + { + SigSpec t = module->Mux(NEW_ID, past_q, sig_d, sig_en); + SigSpec arst = wrap_async_control(module, cell->getPort(ID::ARST), cell->parameters[ID::ARST_POLARITY].as_bool()); + Const rstval = cell->parameters[ID::ARST_VALUE]; + + module->addMux(NEW_ID, t, rstval, arst, sig_q); } else { - SigSpec t; - if (enpol) - t = module->Mux(NEW_ID, past_q, sig_d, sig_en); - else - t = module->Mux(NEW_ID, sig_d, past_q, sig_en); - - SigSpec s = cell->getPort(ID::SET); - if (!cell->parameters[ID::SET_POLARITY].as_bool()) - s = module->Not(NEW_ID, s); + SigSpec t = module->Mux(NEW_ID, past_q, sig_d, sig_en); + + SigSpec s = wrap_async_control(module, cell->getPort(ID::SET), cell->parameters[ID::SET_POLARITY].as_bool()); t = module->Or(NEW_ID, t, s); - SigSpec c = cell->getPort(ID::CLR); - if (cell->parameters[ID::CLR_POLARITY].as_bool()) - c = module->Not(NEW_ID, c); + SigSpec c = wrap_async_control(module, cell->getPort(ID::CLR), cell->parameters[ID::CLR_POLARITY].as_bool()); + c = module->Not(NEW_ID, c); module->addAnd(NEW_ID, t, c, sig_q); } @@ -279,55 +303,30 @@ struct Clk2fflogicPass : public Pass { if (cell->type == ID($adff)) { - SigSpec arst = cell->getPort(ID::ARST); + SigSpec arst = wrap_async_control(module, cell->getPort(ID::ARST), cell->parameters[ID::ARST_POLARITY].as_bool()); SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge); Const rstval = cell->parameters[ID::ARST_VALUE]; - Wire *past_arst = module->addWire(NEW_ID); - module->addFf(NEW_ID, arst, past_arst); - if (cell->parameters[ID::ARST_POLARITY].as_bool()) - arst = module->LogicOr(NEW_ID, arst, past_arst); - else - arst = module->LogicAnd(NEW_ID, arst, past_arst); - - if (cell->parameters[ID::ARST_POLARITY].as_bool()) - module->addMux(NEW_ID, qval, rstval, arst, sig_q); - else - module->addMux(NEW_ID, rstval, qval, arst, sig_q); + module->addMux(NEW_ID, qval, rstval, arst, sig_q); } else if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_))) { - SigSpec arst = cell->getPort(ID::R); + SigSpec arst = wrap_async_control_gate(module, cell->getPort(ID::R), cell->type[7] == 'P'); SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge); SigBit rstval = (cell->type[8] == '1'); - Wire *past_arst = module->addWire(NEW_ID); - module->addFfGate(NEW_ID, arst, past_arst); - if (cell->type[7] == 'P') - arst = module->OrGate(NEW_ID, arst, past_arst); - else - arst = module->AndGate(NEW_ID, arst, past_arst); - - if (cell->type[7] == 'P') - module->addMuxGate(NEW_ID, qval, rstval, arst, sig_q); - else - module->addMuxGate(NEW_ID, rstval, qval, arst, sig_q); + module->addMuxGate(NEW_ID, qval, rstval, arst, sig_q); } else if (cell->type == ID($dffsr)) { SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge); - SigSpec setval = cell->getPort(ID::SET); - SigSpec clrval = cell->getPort(ID::CLR); - - if (!cell->parameters[ID::SET_POLARITY].as_bool()) - setval = module->Not(NEW_ID, setval); - - if (cell->parameters[ID::CLR_POLARITY].as_bool()) - clrval = module->Not(NEW_ID, clrval); + SigSpec setval = wrap_async_control(module, cell->getPort(ID::SET), cell->parameters[ID::SET_POLARITY].as_bool()); + SigSpec clrval = wrap_async_control(module, cell->getPort(ID::CLR), cell->parameters[ID::CLR_POLARITY].as_bool()); + clrval = module->Not(NEW_ID, clrval); qval = module->Or(NEW_ID, qval, setval); module->addAnd(NEW_ID, qval, clrval, sig_q); } @@ -336,15 +335,10 @@ struct Clk2fflogicPass : public Pass { ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_))) { SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge); - SigSpec setval = cell->getPort(ID::S); - SigSpec clrval = cell->getPort(ID::R); - - if (cell->type[9] != 'P') - setval = module->Not(NEW_ID, setval); - - if (cell->type[10] == 'P') - clrval = module->Not(NEW_ID, clrval); + SigSpec setval = wrap_async_control_gate(module, cell->getPort(ID::S), cell->type[9] == 'P'); + SigSpec clrval = wrap_async_control_gate(module, cell->getPort(ID::R), cell->type[10] == 'P'); + clrval = module->NotGate(NEW_ID, clrval); qval = module->OrGate(NEW_ID, qval, setval); module->addAndGate(NEW_ID, qval, clrval, sig_q); } diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 127f8934e..e99c56d8d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -294,7 +294,7 @@ struct Abc9Pass : public ScriptPass run("design -load $abc9_map"); run("proc"); run("wbflip"); - run("techmap"); + run("techmap -wb -map %$abc9 -map +/techmap.v A:abc9_flop"); run("opt"); if (dff_mode || help_mode) { if (!help_mode) diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index 451325fee..1cbd12e3d 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -2,7 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * Copyright (C) 2019 Marcin Kościelnicki <mwk@0x04.net> + * Copyright (C) 2019 Marcelina Kościelnicka <mwk@0x04.net> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -34,33 +34,34 @@ void split_portname_pair(std::string &port1, std::string &port2) } struct ClkbufmapPass : public Pass { - ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { } + ClkbufmapPass() : Pass("clkbufmap", "insert clock buffers on clock networks") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" clkbufmap [options] [selection]\n"); log("\n"); - log("Inserts global buffers between nets connected to clock inputs and their drivers.\n"); + log("Inserts clock buffers between nets connected to clock inputs and their drivers.\n"); log("\n"); log("In the absence of any selection, all wires without the 'clkbuf_inhibit'\n"); - log("attribute will be considered for global buffer insertion.\n"); + log("attribute will be considered for clock buffer insertion.\n"); log("Alternatively, to consider all wires without the 'buffer_type' attribute set to\n"); log("'none' or 'bufr' one would specify:\n"); log(" 'w:* a:buffer_type=none a:buffer_type=bufr %%u %%d'\n"); log("as the selection.\n"); log("\n"); log(" -buf <celltype> <portname_out>:<portname_in>\n"); - log(" Specifies the cell type to use for the global buffers\n"); + log(" Specifies the cell type to use for the clock buffers\n"); log(" and its port names. The first port will be connected to\n"); log(" the clock network sinks, and the second will be connected\n"); - log(" to the actual clock source. This option is required.\n"); + log(" to the actual clock source.\n"); log("\n"); log(" -inpad <celltype> <portname_out>:<portname_in>\n"); log(" If specified, a PAD cell of the given type is inserted on\n"); log(" clock nets that are also top module's inputs (in addition\n"); - log(" to the global buffer).\n"); + log(" to the clock buffer, if any).\n"); log("\n"); + log("At least one of -buf or -inpad should be specified.\n"); } void module_queue(Design *design, Module *module, std::vector<Module *> &modules_sorted, pool<Module *> &modules_processed) { @@ -78,7 +79,7 @@ struct ClkbufmapPass : public Pass { void execute(std::vector<std::string> args, RTLIL::Design *design) override { - log_header(design, "Executing CLKBUFMAP pass (inserting global clock buffers).\n"); + log_header(design, "Executing CLKBUFMAP pass (inserting clock buffers).\n"); std::string buf_celltype, buf_portname, buf_portname2; std::string inpad_celltype, inpad_portname, inpad_portname2; @@ -109,8 +110,8 @@ struct ClkbufmapPass : public Pass { extra_args(args, argidx, design); } - if (buf_celltype.empty()) - log_error("The -buf option is required.\n"); + if (buf_celltype.empty() && inpad_celltype.empty()) + log_error("Either the -buf option or -inpad option is required.\n"); // Cell type, port name, bit index. pool<pair<IdString, pair<IdString, int>>> sink_ports; @@ -118,6 +119,16 @@ struct ClkbufmapPass : public Pass { dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_out; dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_in; + // If true, use both ther -buf and -inpad cell for input ports that are clocks. + bool buffer_inputs = true; + + Module *inpad_mod = design->module(RTLIL::escape_id(inpad_celltype)); + if (inpad_mod) { + Wire *buf_wire = inpad_mod->wire(RTLIL::escape_id(buf_portname)); + if (buf_wire && buf_wire->get_bool_attribute(ID::clkbuf_driver)) + buffer_inputs = false; + } + // Process submodules before module using them. std::vector<Module *> modules_sorted; pool<Module *> modules_processed; @@ -242,19 +253,30 @@ struct ClkbufmapPass : public Pass { // Clock network not yet buffered, driven by one of // our cells or a top-level input -- buffer it. - log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i); - RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype)); - Wire *iwire = module->addWire(NEW_ID); - cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit); - cell->setPort(RTLIL::escape_id(buf_portname2), iwire); - if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top)) { + Wire *iwire = nullptr; + RTLIL::Cell *cell = nullptr; + bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top); + if (!buf_celltype.empty() && (!is_input || buffer_inputs)) { + log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i); + cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype)); + iwire = module->addWire(NEW_ID); + cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit); + cell->setPort(RTLIL::escape_id(buf_portname2), iwire); + } + if (is_input) { log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i); RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype)); - cell2->setPort(RTLIL::escape_id(inpad_portname), iwire); + if (iwire) { + cell2->setPort(RTLIL::escape_id(inpad_portname), iwire); + } else { + cell2->setPort(RTLIL::escape_id(inpad_portname), mapped_wire_bit); + cell = cell2; + } iwire = module->addWire(NEW_ID); cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire); } - buffered_bits[mapped_wire_bit] = make_pair(cell, iwire); + if (iwire) + buffered_bits[mapped_wire_bit] = make_pair(cell, iwire); if (wire->port_input) { input_bits.insert(i); diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 7f2cdc6ac..13ce4f49a 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -364,7 +364,7 @@ flip_dqi: // Some DFF is supported with this init val. Just pick a type. if (ff_type == FF_DFF) { // Try adding a set or reset pin. - for (auto new_type: {FF_ADFF0, FF_ADFF1, FF_SDFF0, FF_SDFF1}) + for (auto new_type: {FF_SDFF0, FF_SDFF1, FF_ADFF0, FF_ADFF1}) if (supported_cells[new_type] & initmask) { ff_type = new_type; sig_r = State::S0; @@ -529,7 +529,7 @@ unmap_enable: } if (supported_dffsr & flip_initmask(initmask)) { flip_dqisr:; - log_warning("Flipping D/Q/init and inseerting set/reset fixup to handle init value on %s.%s [%s]\n", log_id(cell->module->name), log_id(cell->name), log_id(cell->type)); + log_warning("Flipping D/Q/init and inserting set/reset fixup to handle init value on %s.%s [%s]\n", log_id(cell->module->name), log_id(cell->name), log_id(cell->type)); SigSpec new_r; bool neg_r = (ff_neg & NEG_R); bool neg_s = (ff_neg & NEG_S); @@ -659,6 +659,24 @@ flip_dqisr:; // This init value is not supported at all... if (supported_dlatch & flip_initmask(initmask)) goto flip_dqi; + + if ((sig_d == State::S0 && (supported_adff0 & initmask)) || + (sig_d == State::S1 && (supported_adff1 & initmask)) || + (sig_d == State::S0 && (supported_adff1 & flip_initmask(initmask))) || + (sig_d == State::S1 && (supported_adff0 & flip_initmask(initmask))) + ) { + // Special case: const-D dlatch can be converted into adff with const clock. + ff_type = (sig_d == State::S0) ? FF_ADFF0 : FF_ADFF1; + if (ff_neg & NEG_E) { + ff_neg &= ~NEG_E; + ff_neg |= NEG_R; + } + sig_r = sig_e; + sig_d = State::Sx; + sig_c = State::S1; + continue; + } + if (!supported_dlatch) reason = "dlatch are not supported"; else @@ -1278,7 +1296,7 @@ unrecognized: sigmap.set(module); initbits.clear(); - for (auto wire : module->selected_wires()) + for (auto wire : module->wires()) { if (wire->attributes.count(ID::init) == 0) continue; diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index c189d649b..78a6f1c0d 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -115,7 +115,7 @@ static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, return false; } -static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool prepare_mode) +static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval) { LibertyAst *best_cell = nullptr; std::map<std::string, char> best_cell_ports; @@ -222,21 +222,12 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has if (best_cell != nullptr) { log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n", best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str()); - if (prepare_mode) { - cell_mappings[cell_type].cell_name = cell_type; - cell_mappings[cell_type].ports["C"] = 'C'; - if (has_reset) - cell_mappings[cell_type].ports["R"] = 'R'; - cell_mappings[cell_type].ports["D"] = 'D'; - cell_mappings[cell_type].ports["Q"] = 'Q'; - } else { - cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]); - cell_mappings[cell_type].ports = best_cell_ports; - } + cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]); + cell_mappings[cell_type].ports = best_cell_ports; } } -static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool prepare_mode) +static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol) { LibertyAst *best_cell = nullptr; std::map<std::string, char> best_cell_ports; @@ -339,141 +330,12 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool if (best_cell != nullptr) { log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n", best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str()); - if (prepare_mode) { - cell_mappings[cell_type].cell_name = cell_type; - cell_mappings[cell_type].ports["C"] = 'C'; - cell_mappings[cell_type].ports["S"] = 'S'; - cell_mappings[cell_type].ports["R"] = 'R'; - cell_mappings[cell_type].ports["D"] = 'D'; - cell_mappings[cell_type].ports["Q"] = 'Q'; - } else { - cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]); - cell_mappings[cell_type].ports = best_cell_ports; - } + cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]); + cell_mappings[cell_type].ports = best_cell_ports; } } -static bool expand_cellmap_worker(std::string from, std::string to, std::string inv) -{ - if (cell_mappings.count(to) > 0) - return false; - - log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str()); - cell_mappings[to].cell_name = cell_mappings[from].cell_name; - cell_mappings[to].ports = cell_mappings[from].ports; - - for (auto &it : cell_mappings[to].ports) { - char cmp_ch = it.second; - if ('a' <= cmp_ch && cmp_ch <= 'z') - cmp_ch -= 'a' - 'A'; - if (inv.find(cmp_ch) == std::string::npos) - continue; - if ('a' <= it.second && it.second <= 'z') - it.second -= 'a' - 'A'; - else if ('A' <= it.second && it.second <= 'Z') - it.second += 'a' - 'A'; - } - return true; -} - -static bool expand_cellmap(std::string pattern, std::string inv) -{ - std::vector<std::pair<std::string, std::string>> from_to_list; - bool return_status = false; - - for (auto &it : cell_mappings) { - std::string from = it.first.str(), to = it.first.str(); - if (from.size() != pattern.size()) - continue; - for (size_t i = 0; i < from.size(); i++) { - if (pattern[i] == '*') { - to[i] = from[i] == 'P' ? 'N' : - from[i] == 'N' ? 'P' : - from[i] == '1' ? '0' : - from[i] == '0' ? '1' : '*'; - } else - if (pattern[i] != '?' && pattern[i] != from[i]) - goto pattern_failed; - } - from_to_list.push_back(std::pair<std::string, std::string>(from, to)); - pattern_failed:; - } - - for (auto &it : from_to_list) - return_status = return_status || expand_cellmap_worker(it.first, it.second, inv); - return return_status; -} - -static void map_sr_to_arst(IdString from, IdString to) -{ - if (!cell_mappings.count(from) || cell_mappings.count(to) > 0) - return; - - char from_clk_pol = from[8]; - char from_set_pol = from[9]; - char from_clr_pol = from[10]; - char to_clk_pol = to[6]; - char to_rst_pol = to[7]; - char to_rst_val = to[8]; - - log_assert(from_clk_pol == to_clk_pol); - log_assert(to_rst_pol == from_set_pol && to_rst_pol == from_clr_pol); - - log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str()); - cell_mappings[to].cell_name = cell_mappings[from].cell_name; - cell_mappings[to].ports = cell_mappings[from].ports; - - for (auto &it : cell_mappings[to].ports) - { - bool is_set_pin = it.second == 'S' || it.second == 's'; - bool is_clr_pin = it.second == 'R' || it.second == 'r'; - - if (!is_set_pin && !is_clr_pin) - continue; - - if ((to_rst_val == '0' && is_set_pin) || (to_rst_val == '1' && is_clr_pin)) - { - // this is the unused set/clr pin -- deactivate it - if (is_set_pin) - it.second = (from_set_pol == 'P') == (it.second == 'S') ? '0' : '1'; - else - it.second = (from_clr_pol == 'P') == (it.second == 'R') ? '0' : '1'; - } - else - { - // this is the used set/clr pin -- rename it to 'reset' - if (it.second == 'S') - it.second = 'R'; - if (it.second == 's') - it.second = 'r'; - } - } -} - -static void map_adff_to_dff(IdString from, IdString to) -{ - if (!cell_mappings.count(from) || cell_mappings.count(to) > 0) - return; - - char from_clk_pol = from[6]; - char from_rst_pol = from[7]; - char to_clk_pol = to[6]; - - log_assert(from_clk_pol == to_clk_pol); - - log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str()); - cell_mappings[to].cell_name = cell_mappings[from].cell_name; - cell_mappings[to].ports = cell_mappings[from].ports; - - for (auto &it : cell_mappings[to].ports) { - if (it.second == 'S' || it.second == 'R') - it.second = from_rst_pol == 'P' ? '0' : '1'; - if (it.second == 's' || it.second == 'r') - it.second = from_rst_pol == 'P' ? '1' : '0'; - } -} - -static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare_mode) +static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) { log("Mapping DFF cells in module `%s':\n", module->name.c_str()); @@ -499,7 +361,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare module->remove(cell); cell_mapping &cm = cell_mappings[cell_type]; - RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : cm.cell_name); + RTLIL::Cell *new_cell = module->addCell(cell_name, cm.cell_name); new_cell->set_src_attribute(src); @@ -552,7 +414,7 @@ struct DfflibmapPass : public Pass { void help() override { log("\n"); - log(" dfflibmap [-prepare] -liberty <file> [selection]\n"); + log(" dfflibmap [-prepare] [-map-only] [-info] -liberty <file> [selection]\n"); log("\n"); log("Map internal flip-flop cells to the flip-flop cells in the technology\n"); log("library specified in the given liberty file.\n"); @@ -562,15 +424,27 @@ struct DfflibmapPass : public Pass { log("\n"); log("When called with -prepare, this command will convert the internal FF cells\n"); log("to the internal cell types that best match the cells found in the given\n"); - log("liberty file.\n"); + log("liberty file, but won't actually map them to the target cells.\n"); + log("\n"); + log("When called with -map-only, this command will only map internal cell\n"); + log("types that are already of exactly the right type to match the target\n"); + log("cells, leaving remaining internal cells untouched.\n"); + log("\n"); + log("When called with -info, this command will only print the target cell\n"); + log("list, along with their associated internal cell types, and the arguments"); + log("that would be passed to the dfflegalize pass. The design will not be\n"); + log("changed.\n"); log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) override { log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n"); + log_push(); std::string liberty_file; bool prepare_mode = false; + bool map_only_mode = false; + bool info_mode = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -585,10 +459,28 @@ struct DfflibmapPass : public Pass { prepare_mode = true; continue; } + if (arg == "-map-only") { + map_only_mode = true; + continue; + } + if (arg == "-info") { + info_mode = true; + continue; + } break; } extra_args(args, argidx, design); + int modes = 0; + if (prepare_mode) + modes++; + if (map_only_mode) + modes++; + if (info_mode) + modes++; + if (modes > 1) + log_cmd_error("Only one of -prepare, -map-only, or -info options should be given!\n"); + if (liberty_file.empty()) log_cmd_error("Missing `-liberty liberty_file' option!\n"); @@ -599,74 +491,49 @@ struct DfflibmapPass : public Pass { LibertyParser libparser(f); f.close(); - find_cell(libparser.ast, ID($_DFF_N_), false, false, false, false, prepare_mode); - find_cell(libparser.ast, ID($_DFF_P_), true, false, false, false, prepare_mode); - - find_cell(libparser.ast, ID($_DFF_NN0_), false, true, false, false, prepare_mode); - find_cell(libparser.ast, ID($_DFF_NN1_), false, true, false, true, prepare_mode); - find_cell(libparser.ast, ID($_DFF_NP0_), false, true, true, false, prepare_mode); - find_cell(libparser.ast, ID($_DFF_NP1_), false, true, true, true, prepare_mode); - find_cell(libparser.ast, ID($_DFF_PN0_), true, true, false, false, prepare_mode); - find_cell(libparser.ast, ID($_DFF_PN1_), true, true, false, true, prepare_mode); - find_cell(libparser.ast, ID($_DFF_PP0_), true, true, true, false, prepare_mode); - find_cell(libparser.ast, ID($_DFF_PP1_), true, true, true, true, prepare_mode); - - find_cell_sr(libparser.ast, ID($_DFFSR_NNN_), false, false, false, prepare_mode); - find_cell_sr(libparser.ast, ID($_DFFSR_NNP_), false, false, true, prepare_mode); - find_cell_sr(libparser.ast, ID($_DFFSR_NPN_), false, true, false, prepare_mode); - find_cell_sr(libparser.ast, ID($_DFFSR_NPP_), false, true, true, prepare_mode); - find_cell_sr(libparser.ast, ID($_DFFSR_PNN_), true, false, false, prepare_mode); - find_cell_sr(libparser.ast, ID($_DFFSR_PNP_), true, false, true, prepare_mode); - find_cell_sr(libparser.ast, ID($_DFFSR_PPN_), true, true, false, prepare_mode); - find_cell_sr(libparser.ast, ID($_DFFSR_PPP_), true, true, true, prepare_mode); - - // try to implement as many cells as possible just by inverting - // the SET and RESET pins. If necessary, implement cell types - // by inverting both D and Q. Only invert clock pins if there - // is no other way of implementing the cell. - while (1) - { - if (expand_cellmap("$_DFF_?*?_", "R") || - expand_cellmap("$_DFFSR_?*?_", "S") || - expand_cellmap("$_DFFSR_??*_", "R")) - continue; - - if (expand_cellmap("$_DFF_??*_", "DQ")) - continue; - - if (expand_cellmap("$_DFF_*_", "C") || - expand_cellmap("$_DFF_*??_", "C") || - expand_cellmap("$_DFFSR_*??_", "C")) - continue; - - break; - } - - map_sr_to_arst(ID($_DFFSR_NNN_), ID($_DFF_NN0_)); - map_sr_to_arst(ID($_DFFSR_NNN_), ID($_DFF_NN1_)); - map_sr_to_arst(ID($_DFFSR_NPP_), ID($_DFF_NP0_)); - map_sr_to_arst(ID($_DFFSR_NPP_), ID($_DFF_NP1_)); - map_sr_to_arst(ID($_DFFSR_PNN_), ID($_DFF_PN0_)); - map_sr_to_arst(ID($_DFFSR_PNN_), ID($_DFF_PN1_)); - map_sr_to_arst(ID($_DFFSR_PPP_), ID($_DFF_PP0_)); - map_sr_to_arst(ID($_DFFSR_PPP_), ID($_DFF_PP1_)); - - map_adff_to_dff(ID($_DFF_NN0_), ID($_DFF_N_)); - map_adff_to_dff(ID($_DFF_NN1_), ID($_DFF_N_)); - map_adff_to_dff(ID($_DFF_NP0_), ID($_DFF_N_)); - map_adff_to_dff(ID($_DFF_NP1_), ID($_DFF_N_)); - map_adff_to_dff(ID($_DFF_PN0_), ID($_DFF_P_)); - map_adff_to_dff(ID($_DFF_PN1_), ID($_DFF_P_)); - map_adff_to_dff(ID($_DFF_PP0_), ID($_DFF_P_)); - map_adff_to_dff(ID($_DFF_PP1_), ID($_DFF_P_)); + find_cell(libparser.ast, ID($_DFF_N_), false, false, false, false); + find_cell(libparser.ast, ID($_DFF_P_), true, false, false, false); + + find_cell(libparser.ast, ID($_DFF_NN0_), false, true, false, false); + find_cell(libparser.ast, ID($_DFF_NN1_), false, true, false, true); + find_cell(libparser.ast, ID($_DFF_NP0_), false, true, true, false); + find_cell(libparser.ast, ID($_DFF_NP1_), false, true, true, true); + find_cell(libparser.ast, ID($_DFF_PN0_), true, true, false, false); + find_cell(libparser.ast, ID($_DFF_PN1_), true, true, false, true); + find_cell(libparser.ast, ID($_DFF_PP0_), true, true, true, false); + find_cell(libparser.ast, ID($_DFF_PP1_), true, true, true, true); + + find_cell_sr(libparser.ast, ID($_DFFSR_NNN_), false, false, false); + find_cell_sr(libparser.ast, ID($_DFFSR_NNP_), false, false, true); + find_cell_sr(libparser.ast, ID($_DFFSR_NPN_), false, true, false); + find_cell_sr(libparser.ast, ID($_DFFSR_NPP_), false, true, true); + find_cell_sr(libparser.ast, ID($_DFFSR_PNN_), true, false, false); + find_cell_sr(libparser.ast, ID($_DFFSR_PNP_), true, false, true); + find_cell_sr(libparser.ast, ID($_DFFSR_PPN_), true, true, false); + find_cell_sr(libparser.ast, ID($_DFFSR_PPP_), true, true, true); log(" final dff cell mappings:\n"); logmap_all(); - for (auto module : design->selected_modules()) - if (!module->get_blackbox_attribute()) - dfflibmap(design, module, prepare_mode); + if (!map_only_mode) { + std::string dfflegalize_cmd = "dfflegalize"; + for (auto it : cell_mappings) + dfflegalize_cmd += stringf(" -cell %s 01", it.first.c_str()); + dfflegalize_cmd += " t:$_DFF* t:$_SDFF*"; + if (info_mode) { + log("dfflegalize command line: %s\n", dfflegalize_cmd.c_str()); + } else { + Pass::call(design, dfflegalize_cmd); + } + } + + if (!prepare_mode && !info_mode) { + for (auto module : design->selected_modules()) + if (!module->get_blackbox_attribute()) + dfflibmap(design, module); + } + log_pop(); cell_mappings.clear(); } } DfflibmapPass; diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc index 9b350456f..11463380c 100644 --- a/passes/techmap/extractinv.cc +++ b/passes/techmap/extractinv.cc @@ -2,7 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * Copyright (C) 2019 Marcin Kościelnicki <mwk@0x04.net> + * Copyright (C) 2019 Marcelina Kościelnicka <mwk@0x04.net> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above |