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-rw-r--r--passes/cmds/Makefile.inc1
-rw-r--r--passes/cmds/add.cc18
-rw-r--r--passes/cmds/portlist.cc93
-rw-r--r--passes/cmds/show.cc8
-rw-r--r--passes/equiv/equiv_opt.cc12
-rw-r--r--passes/hierarchy/hierarchy.cc24
-rw-r--r--passes/opt/opt_expr.cc4
-rw-r--r--passes/opt/opt_share.cc7
-rw-r--r--passes/pmgen/Makefile.inc1
-rw-r--r--passes/pmgen/README.md2
-rw-r--r--passes/pmgen/peepopt.cc1
-rw-r--r--passes/pmgen/peepopt_dffmux.pmg113
-rw-r--r--passes/techmap/Makefile.inc1
-rw-r--r--passes/techmap/abc9.cc58
-rw-r--r--passes/techmap/alumacc.cc19
-rw-r--r--passes/techmap/dff2dffs.cc29
-rw-r--r--passes/techmap/extractinv.cc123
-rw-r--r--passes/techmap/techmap.cc175
-rw-r--r--passes/tests/test_autotb.cc3
19 files changed, 624 insertions, 68 deletions
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index c8067a8be..cf9663d1d 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -25,6 +25,7 @@ OBJS += passes/cmds/plugin.o
OBJS += passes/cmds/check.o
OBJS += passes/cmds/qwp.o
OBJS += passes/cmds/edgetypes.o
+OBJS += passes/cmds/portlist.o
OBJS += passes/cmds/chformal.o
OBJS += passes/cmds/chtype.o
OBJS += passes/cmds/blackbox.o
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index af6f7043d..dd05ac81f 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -105,6 +105,11 @@ struct AddPass : public Pass {
log("Like 'add -input', but also connect the signal between instances of the\n");
log("selected modules.\n");
log("\n");
+ log("\n");
+ log(" add -mod <name[s]>\n");
+ log("\n");
+ log("Add module[s] with the specified name[s].\n");
+ log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
@@ -113,6 +118,7 @@ struct AddPass : public Pass {
bool arg_flag_input = false;
bool arg_flag_output = false;
bool arg_flag_global = false;
+ bool mod_mode = false;
int arg_width = 0;
size_t argidx;
@@ -133,8 +139,20 @@ struct AddPass : public Pass {
arg_width = atoi(args[++argidx].c_str());
continue;
}
+ if (arg == "-mod") {
+ mod_mode = true;
+ argidx++;
+ break;
+ }
break;
}
+
+ if (mod_mode) {
+ for (; argidx < args.size(); argidx++)
+ design->addModule(RTLIL::escape_id(args[argidx]));
+ return;
+ }
+
extra_args(args, argidx, design);
for (auto &mod : design->modules_)
diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc
new file mode 100644
index 000000000..38c4a8597
--- /dev/null
+++ b/passes/cmds/portlist.cc
@@ -0,0 +1,93 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct PortlistPass : public Pass {
+ PortlistPass() : Pass("portlist", "list (top-level) ports") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" portlist [options] [selection]\n");
+ log("\n");
+ log("This command lists all module ports found in the selected modules.\n");
+ log("\n");
+ log("If no selection is provided then it lists the ports on the top module.\n");
+ log("\n");
+ log(" -m\n");
+ log(" print verilog blackbox module definitions instead of port lists\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ bool m_mode = false;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ if (args[argidx] == "-m") {
+ m_mode = true;
+ continue;
+ }
+ break;
+ }
+
+ bool first_module = true;
+
+ auto handle_module = [&](RTLIL::Module *module) {
+ vector<string> ports;
+ if (first_module)
+ first_module = false;
+ else
+ log("\n");
+ for (auto port : module->ports) {
+ auto *w = module->wire(port);
+ ports.push_back(stringf("%s [%d:%d] %s", w->port_input ? w->port_output ? "inout" : "input" : "output",
+ w->upto ? w->start_offset : w->start_offset + w->width - 1,
+ w->upto ? w->start_offset + w->width - 1 : w->start_offset,
+ log_id(w)));
+ }
+ log("module %s%s\n", log_id(module), m_mode ? " (" : "");
+ for (int i = 0; i < GetSize(ports); i++)
+ log("%s%s\n", ports[i].c_str(), m_mode && i+1 < GetSize(ports) ? "," : "");
+ if (m_mode)
+ log(");\nendmodule\n");
+ };
+
+ if (argidx == args.size())
+ {
+ auto *top = design->top_module();
+ if (top == nullptr)
+ log_cmd_error("Can't find top module in current design!\n");
+ handle_module(top);
+ }
+ else
+ {
+ extra_args(args, argidx, design);
+ for (auto module : design->selected_modules())
+ handle_module(module);
+ }
+ }
+} PortlistPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 2e9fc72af..a3e969ef1 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -26,6 +26,10 @@
# include <dirent.h>
#endif
+#ifdef __APPLE__
+# include <unistd.h>
+#endif
+
#ifdef YOSYS_ENABLE_READLINE
# include <readline/readline.h>
#endif
@@ -866,7 +870,11 @@ struct ShowPass : public Pass {
log_cmd_error("Shell command failed!\n");
} else
if (format.empty()) {
+ #ifdef __APPLE__
+ std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' &", getuid(), dot_file.c_str(), dot_file.c_str());
+ #else
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid'; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' &", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str());
+ #endif
log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc
index 19d1c25ac..d4c7f7953 100644
--- a/passes/equiv/equiv_opt.cc
+++ b/passes/equiv/equiv_opt.cc
@@ -46,6 +46,9 @@ struct EquivOptPass:public ScriptPass
log(" -assert\n");
log(" produce an error if the circuits are not equivalent.\n");
log("\n");
+ log(" -multiclock\n");
+ log(" run clk2fflogic before equivalence checking.\n");
+ log("\n");
log(" -undef\n");
log(" enable modelling of undef states during equiv_induct.\n");
log("\n");
@@ -55,7 +58,7 @@ struct EquivOptPass:public ScriptPass
}
std::string command, techmap_opts;
- bool assert, undef;
+ bool assert, undef, multiclock;
void clear_flags() YS_OVERRIDE
{
@@ -63,6 +66,7 @@ struct EquivOptPass:public ScriptPass
techmap_opts = "";
assert = false;
undef = false;
+ multiclock = false;
}
void execute(std::vector < std::string > args, RTLIL::Design * design) YS_OVERRIDE
@@ -92,6 +96,10 @@ struct EquivOptPass:public ScriptPass
undef = true;
continue;
}
+ if (args[argidx] == "-multiclock") {
+ multiclock = true;
+ continue;
+ }
break;
}
@@ -146,6 +154,8 @@ struct EquivOptPass:public ScriptPass
}
if (check_label("prove")) {
+ if (multiclock || help_mode)
+ run("clk2fflogic", "(only with -multiclock)");
run("equiv_make gold gate equiv");
if (help_mode)
run("equiv_induct [-undef] equiv");
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index fd95b94b2..d8a628448 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -808,6 +808,30 @@ struct HierarchyPass : public Pass {
if (mod_it.second->get_bool_attribute("\\top"))
top_mod = mod_it.second;
+ if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
+ IdString top_name = top_mod->name.substr(strlen("$abstract"));
+
+ dict<RTLIL::IdString, RTLIL::Const> top_parameters;
+ for (auto &para : parameters) {
+ SigSpec sig_value;
+ if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second))
+ log_cmd_error("Can't decode value '%s'!\n", para.second.c_str());
+ top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const();
+ }
+
+ top_mod = design->module(top_mod->derive(design, top_parameters));
+
+ if (top_mod != nullptr && top_mod->name != top_name) {
+ Module *m = top_mod->clone();
+ m->name = top_name;
+ Module *old_mod = design->module(top_name);
+ if (old_mod)
+ design->remove(old_mod);
+ design->add(m);
+ top_mod = m;
+ }
+ }
+
if (top_mod == nullptr && auto_top_mode) {
log_header(design, "Finding top of design hierarchy..\n");
dict<Module*, int> db;
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 00d7d6063..6cf66fb95 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -953,6 +953,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
if (b.is_fully_const()) {
+ if (b.is_fully_undef()) {
+ RTLIL::SigSpec input = b;
+ ACTION_DO(ID::Y, Const(State::Sx, GetSize(cell->getPort(ID::Y))));
+ } else
if (b.as_bool() == (cell->type == ID($eq))) {
RTLIL::SigSpec input = b;
ACTION_DO(ID::Y, cell->getPort(ID::A));
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index c53fb3113..2c456705c 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -108,12 +108,13 @@ bool cell_supported(RTLIL::Cell *cell)
return false;
}
-std::map<IdString, IdString> mergeable_type_map{
- {ID($sub), ID($add)},
-};
+std::map<IdString, IdString> mergeable_type_map;
bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
{
+ if (mergeable_type_map.empty()) {
+ mergeable_type_map.insert({ID($sub), ID($add)});
+ }
auto a_type = a->type;
if (mergeable_type_map.count(a_type))
a_type = mergeable_type_map.at(a_type);
diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index 4989c582a..98691d0fe 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -27,6 +27,7 @@ $(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h))
PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul.pmg
PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg
+PEEPOPT_PATTERN += passes/pmgen/peepopt_dffmux.pmg
passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
$(P) mkdir -p passes/pmgen && python3 $< -o $@ -p peepopt $(filter-out $<,$^)
diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md
index 0856c9ba3..2f5b8d0b2 100644
--- a/passes/pmgen/README.md
+++ b/passes/pmgen/README.md
@@ -352,7 +352,7 @@ state variables used to pass arguments.
subpattern tail
...
-Subpatterns cann be called recursively.
+Subpatterns can be called recursively.
If a `subpattern` statement is preceded by a `fallthrough` statement, this is
equivalent to calling the subpattern at the end of the preceding block.
diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc
index e7f95cf85..72b02127a 100644
--- a/passes/pmgen/peepopt.cc
+++ b/passes/pmgen/peepopt.cc
@@ -60,6 +60,7 @@ struct PeepoptPass : public Pass {
peepopt_pm pm(module, module->selected_cells());
pm.run_shiftmul();
pm.run_muldiv();
+ pm.run_dffmux();
}
}
}
diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg
new file mode 100644
index 000000000..c88a52226
--- /dev/null
+++ b/passes/pmgen/peepopt_dffmux.pmg
@@ -0,0 +1,113 @@
+pattern dffmux
+
+state <IdString> cemuxAB rstmuxBA
+state <SigSpec> sigD
+
+match dff
+ select dff->type == $dff
+ select GetSize(port(dff, \D)) > 1
+endmatch
+
+match rstmux
+ select rstmux->type == $mux
+ select GetSize(port(rstmux, \Y)) > 1
+ index <SigSpec> port(rstmux, \Y) === port(dff, \D)
+ choice <IdString> BA {\B, \A}
+ select port(rstmux, BA).is_fully_const()
+ set rstmuxBA BA
+ optional
+endmatch
+
+code sigD
+ if (rstmux)
+ sigD = port(rstmux, rstmuxBA == \B ? \A : \B);
+ else
+ sigD = port(dff, \D);
+endcode
+
+match cemux
+ select cemux->type == $mux
+ select GetSize(port(cemux, \Y)) > 1
+ index <SigSpec> port(cemux, \Y) === sigD
+ choice <IdString> AB {\A, \B}
+ index <SigSpec> port(cemux, AB) === port(dff, \Q)
+ set cemuxAB AB
+endmatch
+
+code
+ SigSpec D = port(cemux, cemuxAB == \A ? \B : \A);
+ SigSpec Q = port(dff, \Q);
+ Const rst;
+ if (rstmux)
+ rst = port(rstmux, rstmuxBA).as_const();
+ int width = GetSize(D);
+
+ SigSpec &ceA = cemux->connections_.at(\A);
+ SigSpec &ceB = cemux->connections_.at(\B);
+ SigSpec &ceY = cemux->connections_.at(\Y);
+ SigSpec &dffD = dff->connections_.at(\D);
+ SigSpec &dffQ = dff->connections_.at(\Q);
+
+ if (D[width-1] == D[width-2]) {
+ did_something = true;
+
+ SigBit sign = D[width-1];
+ bool is_signed = sign.wire;
+ int i;
+ for (i = width-1; i >= 2; i--) {
+ if (!is_signed) {
+ module->connect(Q[i], sign);
+ if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1]))
+ break;
+ }
+ else {
+ module->connect(Q[i], Q[i-1]);
+ if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1]))
+ break;
+ }
+ }
+
+ ceA.remove(i, width-i);
+ ceB.remove(i, width-i);
+ ceY.remove(i, width-i);
+ cemux->fixup_parameters();
+ dffD.remove(i, width-i);
+ dffQ.remove(i, width-i);
+ dff->fixup_parameters();
+
+ log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
+ accept;
+ }
+ else {
+ int count = 0;
+ for (int i = width-1; i >= 0; i--) {
+ if (D[i].wire)
+ continue;
+ Wire *w = Q[i].wire;
+ auto it = w->attributes.find(\init);
+ State init;
+ if (it != w->attributes.end())
+ init = it->second[Q[i].offset];
+ else
+ init = State::Sx;
+
+ if (init == State::Sx || init == D[i].data) {
+ count++;
+ module->connect(Q[i], D[i]);
+ ceA.remove(i);
+ ceB.remove(i);
+ ceY.remove(i);
+ dffD.remove(i);
+ dffQ.remove(i);
+ }
+ }
+ if (count > 0) {
+ did_something = true;
+ cemux->fixup_parameters();
+ dff->fixup_parameters();
+ log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count);
+ }
+
+ accept;
+ }
+endcode
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 631a80aa5..cd357d72a 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -40,6 +40,7 @@ OBJS += passes/techmap/attrmap.o
OBJS += passes/techmap/zinit.o
OBJS += passes/techmap/dff2dffs.o
OBJS += passes/techmap/flowmap.o
+OBJS += passes/techmap/extractinv.o
endif
GENFILES += passes/techmap/techmap.inc
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 6fdf987f0..7eac08d17 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -76,8 +76,7 @@ inline std::string remap_name(RTLIL::IdString abc_name)
return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
}
-void handle_loops(RTLIL::Design *design,
- const dict<IdString,pool<IdString>> &scc_break_inputs)
+void handle_loops(RTLIL::Design *design)
{
Pass::call(design, "scc -set_attr abc_scc_id {}");
@@ -114,30 +113,6 @@ void handle_loops(RTLIL::Design *design,
}
cell->attributes.erase(it);
}
-
- auto jt = scc_break_inputs.find(cell->type);
- if (jt != scc_break_inputs.end())
- for (auto port_name : jt->second) {
- RTLIL::SigSpec sig;
- auto &rhs = cell->connections_.at(port_name);
- for (auto b : rhs) {
- Wire *w = b.wire;
- if (!w) continue;
- w->port_output = true;
- w->set_bool_attribute(ID(abc_scc_break));
- w = module->wire(stringf("%s.abci", w->name.c_str()));
- if (!w) {
- w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
- w->port_input = true;
- }
- else {
- log_assert(b.offset < GetSize(w));
- log_assert(w->port_input);
- }
- sig.append(RTLIL::SigBit(w, b.offset));
- }
- rhs = sig;
- }
}
module->fixup_ports();
@@ -272,8 +247,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
bool show_tempdir, std::string box_file, std::string lut_file,
- std::string wire_delay, const dict<int,IdString> &box_lookup,
- const dict<IdString,pool<IdString>> &scc_break_inputs
+ std::string wire_delay, const dict<int,IdString> &box_lookup
)
{
module = current_module;
@@ -413,7 +387,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
- handle_loops(design, scc_break_inputs);
+ handle_loops(design);
Pass::call(design, "aigmap");
@@ -1050,9 +1024,6 @@ struct Abc9Pass : public Pass {
}
if (arg == "-box" && argidx+1 < args.size()) {
box_file = args[++argidx];
- rewrite_filename(box_file);
- if (!box_file.empty() && !is_absolute_path(box_file))
- box_file = std::string(pwd) + "/" + box_file;
continue;
}
if (arg == "-W" && argidx+1 < args.size()) {
@@ -1063,8 +1034,15 @@ struct Abc9Pass : public Pass {
}
extra_args(args, argidx, design);
+ // ABC expects a box file for XAIG
+ if (box_file.empty())
+ box_file = "+/dummy.box";
+
+ rewrite_filename(box_file);
+ if (!box_file.empty() && !is_absolute_path(box_file))
+ box_file = std::string(pwd) + "/" + box_file;
+
dict<int,IdString> box_lookup;
- dict<IdString,pool<IdString>> scc_break_inputs;
for (auto m : design->modules()) {
auto it = m->attributes.find(ID(abc_box_id));
if (it == m->attributes.end())
@@ -1082,17 +1060,13 @@ struct Abc9Pass : public Pass {
for (auto p : m->ports) {
auto w = m->wire(p);
log_assert(w);
- if (w->port_input) {
- if (w->attributes.count(ID(abc_scc_break)))
- scc_break_inputs[m->name].insert(p);
- if (w->attributes.count(ID(abc_carry))) {
+ if (w->attributes.count(ID(abc_carry))) {
+ if (w->port_input) {
if (carry_in)
log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
carry_in = w;
}
- }
- if (w->port_output) {
- if (w->attributes.count(ID(abc_carry))) {
+ else if (w->port_output) {
if (carry_out)
log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
carry_out = w;
@@ -1144,7 +1118,7 @@ struct Abc9Pass : public Pass {
if (!dff_mode || !clk_str.empty()) {
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
delay_target, lutin_shared, fast_mode, show_tempdir,
- box_file, lut_file, wire_delay, box_lookup, scc_break_inputs);
+ box_file, lut_file, wire_delay, box_lookup);
continue;
}
@@ -1290,7 +1264,7 @@ struct Abc9Pass : public Pass {
en_sig = assign_map(std::get<3>(it.first));
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
- box_file, lut_file, wire_delay, box_lookup, scc_break_inputs);
+ box_file, lut_file, wire_delay, box_lookup);
assign_map.set(mod);
}
}
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 5b168d524..034731b87 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -48,14 +48,25 @@ struct AlumaccWorker
RTLIL::SigSpec cached_cf, cached_of, cached_sf;
RTLIL::SigSpec get_lt() {
- if (GetSize(cached_lt) == 0)
- cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf();
+ if (GetSize(cached_lt) == 0) {
+ if (is_signed) {
+ get_of();
+ get_sf();
+ cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf);
+ }
+ else
+ cached_lt = get_cf();
+ }
return cached_lt;
}
RTLIL::SigSpec get_gt() {
- if (GetSize(cached_gt) == 0)
- cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->get_src_attribute());
+ if (GetSize(cached_gt) == 0) {
+ get_lt();
+ get_eq();
+ SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq);
+ cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
+ }
return cached_gt;
}
diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc
index 0ea033513..3fa1ed5cf 100644
--- a/passes/techmap/dff2dffs.cc
+++ b/passes/techmap/dff2dffs.cc
@@ -34,11 +34,16 @@ struct Dff2dffsPass : public Pass {
log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n");
log("dff2dffe for SR over CE priority.\n");
log("\n");
+ log(" -match-init\n");
+ log(" Disallow merging synchronous set/reset that has polarity opposite of the\n");
+ log(" output wire's init attribute (if any).\n");
+ log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n");
+ bool match_init = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
@@ -46,6 +51,10 @@ struct Dff2dffsPass : public Pass {
// singleton_mode = true;
// continue;
// }
+ if (args[argidx] == "-match-init") {
+ match_init = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -96,9 +105,6 @@ struct Dff2dffsPass : public Pass {
SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
SigBit bit_s = sigmap(mux_cell->getPort(ID(S)));
- log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
- log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
-
SigBit sr_val, sr_sig;
bool invert_sr;
sr_sig = bit_s;
@@ -113,6 +119,23 @@ struct Dff2dffsPass : public Pass {
invert_sr = false;
}
+ if (match_init) {
+ SigBit bit_q = cell->getPort(ID(Q));
+ if (bit_q.wire) {
+ auto it = bit_q.wire->attributes.find(ID(init));
+ if (it != bit_q.wire->attributes.end()) {
+ auto init_val = it->second[bit_q.offset];
+ if (init_val == State::S1 && sr_val != State::S1)
+ continue;
+ if (init_val == State::S0 && sr_val != State::S0)
+ continue;
+ }
+ }
+ }
+
+ log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
+ log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
+
if (sr_val == State::S1) {
if (cell->type == ID($_DFF_N_)) {
if (invert_sr) cell->type = ID($__DFFS_NN1_);
diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc
new file mode 100644
index 000000000..dda71f12a
--- /dev/null
+++ b/passes/techmap/extractinv.cc
@@ -0,0 +1,123 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2019 Marcin Kościelnicki <mwk@0x04.net>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void split_portname_pair(std::string &port1, std::string &port2)
+{
+ size_t pos = port1.find_first_of(':');
+ if (pos != std::string::npos) {
+ port2 = port1.substr(pos+1);
+ port1 = port1.substr(0, pos);
+ }
+}
+
+struct ExtractinvPass : public Pass {
+ ExtractinvPass() : Pass("extractinv", "extract explicit inverter cells for invertible cell pins") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" extractinv [options] [selection]\n");
+ log("\n");
+ log("Searches the design for all cells with invertible pins controlled by a cell\n");
+ log("parameter (eg. IS_CLK_INVERTED on many Xilinx cells) and removes the parameter.\n");
+ log("If the parameter was set to 1, inserts an explicit inverter cell in front of\n");
+ log("the pin instead. Normally used for output to ISE, which does not support the\n");
+ log("inversion parameters.\n");
+ log("\n");
+ log("To mark a cell port as invertible, use (* invertible_pin = \"param_name\" *)\n");
+ log("on the wire in the blackbox module. The parameter value should have\n");
+ log("the same width as the port, and will be effectively XORed with it.\n");
+ log("\n");
+ log(" -inv <celltype> <portname_out>:<portname_in>\n");
+ log(" Specifies the cell type to use for the inverters and its port names.\n");
+ log(" This option is required.\n");
+ log("\n");
+ }
+
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing EXTRACTINV pass (extracting pin inverters).\n");
+
+ std::string inv_celltype, inv_portname, inv_portname2;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ std::string arg = args[argidx];
+ if (arg == "-inv" && argidx+2 < args.size()) {
+ inv_celltype = args[++argidx];
+ inv_portname = args[++argidx];
+ split_portname_pair(inv_portname, inv_portname2);
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (inv_celltype.empty())
+ log_error("The -inv option is required.\n");
+
+ for (auto module : design->selected_modules())
+ {
+ for (auto cell : module->selected_cells())
+ for (auto port : cell->connections()) {
+ auto cell_module = design->module(cell->type);
+ if (!cell_module)
+ continue;
+ auto cell_wire = cell_module->wire(port.first);
+ if (!cell_wire)
+ continue;
+ auto it = cell_wire->attributes.find("\\invertible_pin");
+ if (it == cell_wire->attributes.end())
+ continue;
+ IdString param_name = RTLIL::escape_id(it->second.decode_string());
+ auto it2 = cell->parameters.find(param_name);
+ // Inversion not used -- skip.
+ if (it2 == cell->parameters.end())
+ continue;
+ SigSpec sig = port.second;
+ if (it2->second.size() != sig.size())
+ log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", log_id(module->name), log_id(cell->type), log_id(port.first), log_id(param_name));
+ RTLIL::Const invmask = it2->second;
+ cell->parameters.erase(param_name);
+ if (invmask.is_fully_zero())
+ continue;
+ Wire *iwire = module->addWire(NEW_ID, sig.size());
+ for (int i = 0; i < sig.size(); i++)
+ if (invmask[i] == State::S1) {
+ RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype));
+ icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
+ icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
+ log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype.c_str(), log_id(module), log_id(cell->type), log_id(port.first), i);
+ sig[i] = SigBit(iwire, i);
+ }
+ cell->setPort(port.first, sig);
+ }
+ }
+ }
+} ExtractinvPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index c4496f76f..1d0362ad6 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -205,20 +205,57 @@ struct TechmapWorker
}
std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
+ dict<Wire*, IdString> temp_renamed_wires;
+ pool<SigBit> autopurge_tpl_bits;
- for (auto &it : tpl->wires_) {
+ for (auto &it : tpl->wires_)
+ {
if (it.second->port_id > 0)
- positional_ports[stringf("$%d", it.second->port_id)] = it.first;
+ {
+ IdString posportname = stringf("$%d", it.second->port_id);
+ positional_ports[posportname] = it.first;
+
+ if (!flatten_mode && it.second->get_bool_attribute(ID(techmap_autopurge)) &&
+ (!cell->hasPort(it.second->name) || !GetSize(cell->getPort(it.second->name))) &&
+ (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
+ {
+ if (sigmaps.count(tpl) == 0)
+ sigmaps[tpl].set(tpl);
+
+ for (auto bit : sigmaps.at(tpl)(it.second))
+ if (bit.wire != nullptr)
+ autopurge_tpl_bits.insert(bit);
+ }
+ }
IdString w_name = it.second->name;
apply_prefix(cell->name, w_name);
- RTLIL::Wire *w = module->addWire(w_name, it.second);
- w->port_input = false;
- w->port_output = false;
- w->port_id = 0;
- if (it.second->get_bool_attribute(ID(_techmap_special_)))
- w->attributes.clear();
- if (w->attributes.count(ID(src)))
- w->add_strpool_attribute(ID(src), extra_src_attrs);
+ RTLIL::Wire *w = module->wire(w_name);
+ if (w != nullptr) {
+ if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) {
+ temp_renamed_wires[w] = w->name;
+ module->rename(w, NEW_ID);
+ w = nullptr;
+ } else {
+ w->attributes.erase(ID(hierconn));
+ if (GetSize(w) < GetSize(it.second)) {
+ log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
+ log_id(tpl), log_id(it.second), log_id(module), log_id(cell));
+ w->width = GetSize(it.second);
+ }
+ }
+ }
+ if (w == nullptr) {
+ w = module->addWire(w_name, it.second);
+ w->port_input = false;
+ w->port_output = false;
+ w->port_id = 0;
+ if (!flatten_mode)
+ w->attributes.erase(ID(techmap_autopurge));
+ if (it.second->get_bool_attribute(ID(_techmap_special_)))
+ w->attributes.clear();
+ if (w->attributes.count(ID(src)))
+ w->add_strpool_attribute(ID(src), extra_src_attrs);
+ }
design->select(module, w);
}
@@ -322,6 +359,12 @@ struct TechmapWorker
for (auto &attr : w->attributes) {
if (attr.first == ID(src))
continue;
+ auto lhs = GetSize(extra_connect.first);
+ auto rhs = GetSize(extra_connect.second);
+ if (lhs > rhs)
+ extra_connect.first.remove(rhs, lhs-rhs);
+ else if (rhs > lhs)
+ extra_connect.second.remove(lhs, rhs-lhs);
module->connect(extra_connect);
break;
}
@@ -344,11 +387,31 @@ struct TechmapWorker
if (!flatten_mode && c->type.begins_with("\\$"))
c->type = c->type.substr(1);
- for (auto &it2 : c->connections_) {
- apply_prefix(cell->name, it2.second, module);
- port_signal_map.apply(it2.second);
+ vector<IdString> autopurge_ports;
+
+ for (auto &it2 : c->connections_)
+ {
+ bool autopurge = false;
+ if (!autopurge_tpl_bits.empty()) {
+ autopurge = GetSize(it2.second) != 0;
+ for (auto &bit : sigmaps.at(tpl)(it2.second))
+ if (!autopurge_tpl_bits.count(bit)) {
+ autopurge = false;
+ break;
+ }
+ }
+
+ if (autopurge) {
+ autopurge_ports.push_back(it2.first);
+ } else {
+ apply_prefix(cell->name, it2.second, module);
+ port_signal_map.apply(it2.second);
+ }
}
+ for (auto &it2 : autopurge_ports)
+ c->unsetPort(it2);
+
if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
IdString memid = c->getParam(ID(MEMID)).decode_string();
log_assert(memory_renames.count(memid) != 0);
@@ -380,6 +443,16 @@ struct TechmapWorker
}
module->remove(cell);
+
+ for (auto &it : temp_renamed_wires)
+ {
+ Wire *w = it.first;
+ IdString name = it.second;
+ IdString altname = module->uniquify(name);
+ Wire *other_w = module->wire(name);
+ module->rename(other_w, altname);
+ module->rename(w, name);
+ }
}
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
@@ -396,6 +469,18 @@ struct TechmapWorker
SigMap sigmap(module);
+ dict<SigBit, State> init_bits;
+ pool<SigBit> remove_init_bits;
+
+ for (auto wire : module->wires()) {
+ if (wire->attributes.count("\\init")) {
+ Const value = wire->attributes.at("\\init");
+ for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
+ if (value[i] != State::Sx)
+ init_bits[sigmap(SigBit(wire, i))] = value[i];
+ }
+ }
+
TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
@@ -633,6 +718,17 @@ struct TechmapWorker
bit = RTLIL::SigBit(RTLIL::State::Sx);
parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
}
+ if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))) != 0) {
+ auto sig = sigmap(conn.second);
+ RTLIL::Const value(State::Sx, sig.size());
+ for (int i = 0; i < sig.size(); i++) {
+ auto it = init_bits.find(sig[i]);
+ if (it != init_bits.end()) {
+ value[i] = it->second;
+ }
+ }
+ parameters[stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))] = value;
+ }
}
int unique_bit_id_counter = 0;
@@ -833,12 +929,25 @@ struct TechmapWorker
TechmapWires twd = techmap_find_special_wires(tpl);
for (auto &it : twd) {
- if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
+ if (it.first != "_TECHMAP_FAIL_" && (it.first.substr(0, 20) != "_TECHMAP_REMOVEINIT_" || it.first[it.first.size()-1] != '_') && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
if (techmap_do_cache[tpl])
for (auto &it2 : it.second)
if (!it2.value.is_fully_const())
log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
+ if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_" && techmap_do_cache[tpl]) {
+ for (auto &it2 : it.second) {
+ auto val = it2.value.as_const();
+ auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1));
+ auto it = cell->connections().find(wirename);
+ if (it != cell->connections().end()) {
+ auto sig = sigmap(it->second);
+ for (int i = 0; i < sig.size(); i++)
+ if (val[i] == State::S1)
+ remove_init_bits.insert(sig[i]);
+ }
+ }
+ }
techmap_wire_names.erase(it.first);
}
@@ -907,6 +1016,25 @@ struct TechmapWorker
handled_cells.insert(cell);
}
+ if (!remove_init_bits.empty()) {
+ for (auto wire : module->wires())
+ if (wire->attributes.count("\\init")) {
+ Const &value = wire->attributes.at("\\init");
+ bool do_cleanup = true;
+ for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
+ SigBit bit = sigmap(SigBit(wire, i));
+ if (remove_init_bits.count(bit))
+ value[i] = State::Sx;
+ else if (value[i] != State::Sx)
+ do_cleanup = false;
+ }
+ if (do_cleanup) {
+ log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
+ wire->attributes.erase("\\init");
+ }
+ }
+ }
+
if (log_continue) {
log_header(design, "Continuing TECHMAP pass.\n");
log_continue = false;
@@ -981,6 +1109,11 @@ struct TechmapPass : public Pass {
log("will create a wrapper for the cell and then run the command string that the\n");
log("attribute is set to on the wrapper module.\n");
log("\n");
+ log("When a port on a module in the map file has the 'techmap_autopurge' attribute\n");
+ log("set, and that port is not connected in the instantiation that is mapped, then\n");
+ log("then a cell port connected only to such wires will be omitted in the mapped\n");
+ log("version of the circuit.\n");
+ log("\n");
log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
log("the mapping module to the techmap command. At the moment the following special\n");
@@ -1019,6 +1152,13 @@ struct TechmapPass : public Pass {
log("\n");
log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
log("\n");
+ log(" _TECHMAP_REMOVEINIT_<port-name>_\n");
+ log(" When this wire is set to a constant value, the init attribute of the wire(s)\n");
+ log(" connected to this port will be consumed. This wire must have the same\n");
+ log(" width as the given port, and for every bit that is set to 1 in the value,\n");
+ log(" the corresponding init attribute bit will be changed to 1'bx. If all\n");
+ log(" bits of an init attribute are left as x, it will be removed.\n");
+ log("\n");
log("In addition to this special wires, techmap also supports special parameters in\n");
log("modules in the map file:\n");
log("\n");
@@ -1032,6 +1172,13 @@ struct TechmapPass : public Pass {
log(" former has a 1-bit for each constant input bit and the latter has the\n");
log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
log("\n");
+ log(" _TECHMAP_WIREINIT_<port-name>_\n");
+ log(" When a parameter with this name exists, it will be set to the initial\n");
+ log(" value of the wire(s) connected to the given port, as specified by the init\n");
+ log(" attribute. If the attribute doesn't exist, x will be filled for the\n");
+ log(" missing bits. To remove the init attribute bits used, use the\n");
+ log(" _TECHMAP_REMOVEINIT_*_ wires.\n");
+ log("\n");
log(" _TECHMAP_BITS_CONNMAP_\n");
log(" _TECHMAP_CONNMAP_<port-name>_\n");
log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc
index bfb1d6642..a5ac3130f 100644
--- a/passes/tests/test_autotb.cc
+++ b/passes/tests/test_autotb.cc
@@ -345,6 +345,9 @@ struct TestAutotbBackend : public Backend {
log("value after initialization. This can e.g. be used to force a reset signal\n");
log("low in order to explore more inner states in a state machine.\n");
log("\n");
+ log("The attribute 'gentb_skip' can be attached to modules to suppress testbench\n");
+ log("generation.\n");
+ log("\n");
log(" -n <int>\n");
log(" number of iterations the test bench should run (default = 1000)\n");
log("\n");
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-10 21:07:01 +0000