diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/trace.cc | 6 | ||||
| -rw-r--r-- | passes/memory/memory_share.cc | 5 |
2 files changed, 5 insertions, 6 deletions
diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index b4bc45c20..6a5ea346e 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -34,9 +34,9 @@ struct TraceMonitor : public RTLIL::Monitor log("#TRACE# Module delete: %s\n", log_id(module)); } - virtual void notify_cell_connect(RTLIL::Cell *cell, const std::pair<RTLIL::IdString, RTLIL::SigSpec> &conn) override + virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) override { - log("#TRACE# Cell connect: %s.%s.%s = %s\n", log_id(cell->module), log_id(cell), log_id(conn.first), log_signal(conn.second)); + log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); } virtual void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override @@ -44,7 +44,7 @@ struct TraceMonitor : public RTLIL::Monitor log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); } - virtual void notify_new_connections(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) override + virtual void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) override { log("#TRACE# New connections in module %s:\n", log_id(module)); for (auto &sigsig : sigsig_vec) diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index fde6ea007..ace6eeaf1 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -735,9 +735,8 @@ struct MemorySharePass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - MemoryShareWorker(design, mod_it.second); + for (auto module : design->selected_modules()) + MemoryShareWorker(design, module); } } MemorySharePass; |