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-rw-r--r--passes/cmds/bugpoint.cc18
-rw-r--r--passes/cmds/design.cc10
-rw-r--r--passes/hierarchy/hierarchy.cc30
-rw-r--r--passes/sat/sim.cc6
-rw-r--r--passes/techmap/abc9_ops.cc49
5 files changed, 87 insertions, 26 deletions
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
index ad6a07fa0..a75927393 100644
--- a/passes/cmds/bugpoint.cc
+++ b/passes/cmds/bugpoint.cc
@@ -133,6 +133,7 @@ struct BugpointPass : public Pass {
int index = 0;
if (modules)
{
+ Module *removed_module = nullptr;
for (auto module : design_copy->modules())
{
if (module->get_blackbox_attribute())
@@ -141,10 +142,14 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log("Trying to remove module %s.\n", module->name.c_str());
- design_copy->remove(module);
- return design_copy;
+ removed_module = module;
+ break;
}
}
+ if (removed_module) {
+ design_copy->remove(removed_module);
+ return design_copy;
+ }
}
if (ports)
{
@@ -178,15 +183,20 @@ struct BugpointPass : public Pass {
if (mod->get_blackbox_attribute())
continue;
+ Cell *removed_cell = nullptr;
for (auto cell : mod->cells())
{
if (index++ == seed)
{
log("Trying to remove cell %s.%s.\n", mod->name.c_str(), cell->name.c_str());
- mod->remove(cell);
- return design_copy;
+ removed_cell = cell;
+ break;
}
}
+ if (removed_cell) {
+ mod->remove(removed_cell);
+ return design_copy;
+ }
}
}
if (connections)
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index cfe97067d..421defe0c 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -228,14 +228,20 @@ struct DesignPass : public Pass {
}
if (import_mode) {
+ std::vector<RTLIL::Module*> candidates;
for (auto module : copy_src_modules)
{
if (module->get_bool_attribute(ID::top)) {
- copy_src_modules.clear();
- copy_src_modules.push_back(module);
+ candidates.clear();
+ candidates.push_back(module);
break;
}
+ if (!module->get_blackbox_attribute())
+ candidates.push_back(module);
}
+
+ if (GetSize(candidates) == 1)
+ copy_src_modules = std::move(candidates);
}
}
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 3880b19fe..95d74d1eb 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -334,10 +334,16 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));
}
- for (auto &param : cell->parameters)
- if (mod->avail_parameters.count(param.first) == 0 && param.first[0] != '$' && strchr(param.first.c_str(), '.') == NULL)
+ for (auto &param : cell->parameters) {
+ if (param.first[0] == '$' && '0' <= param.first[1] && param.first[1] <= '9') {
+ int id = atoi(param.first.c_str()+1);
+ if (id <= 0 || id > GetSize(mod->avail_parameters))
+ log_error("Module `%s' referenced in module `%s' in cell `%s' has only %d parameters, requested parameter %d.\n",
+ log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->avail_parameters), id);
+ } else if (mod->avail_parameters.count(param.first) == 0 && param.first[0] != '$' && strchr(param.first.c_str(), '.') == NULL)
log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a parameter named '%s'.\n",
log_id(cell->type), log_id(module), log_id(cell), log_id(param.first));
+ }
}
}
@@ -939,7 +945,8 @@ struct HierarchyPass : public Pass {
for (auto mod : design->modules())
for (auto cell : mod->cells()) {
- if (design->module(cell->type) == nullptr)
+ RTLIL::Module *cell_mod = design->module(cell->type);
+ if (cell_mod == nullptr)
continue;
for (auto &conn : cell->connections())
if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
@@ -947,6 +954,23 @@ struct HierarchyPass : public Pass {
pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod, cell));
break;
}
+
+ pool<std::pair<IdString, IdString>> params_rename;
+ for (const auto &p : cell->parameters) {
+ if (p.first[0] == '$' && '0' <= p.first[1] && p.first[1] <= '9') {
+ int id = atoi(p.first.c_str()+1);
+ if (id <= 0 || id > GetSize(cell_mod->avail_parameters)) {
+ log(" Failed to map positional parameter %d of cell %s.%s (%s).\n",
+ id, RTLIL::id2cstr(mod->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
+ } else {
+ params_rename.insert(std::make_pair(p.first, cell_mod->avail_parameters[id - 1]));
+ }
+ }
+ }
+ for (const auto &p : params_rename) {
+ cell->setParam(p.second, cell->getParam(p.first));
+ cell->unsetParam(p.first);
+ }
}
for (auto module : pos_mods)
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 59bf5a712..03ca42cf3 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -128,8 +128,12 @@ struct SimInstance
for (auto &port : cell->connections()) {
if (cell->input(port.first))
- for (auto bit : sigmap(port.second))
+ for (auto bit : sigmap(port.second)) {
upd_cells[bit].insert(cell);
+ // Make sure cell inputs connected to constants are updated in the first cycle
+ if (bit.wire == nullptr)
+ dirty_bits.insert(bit);
+ }
}
if (cell->type.in(ID($dff))) {
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 8ae1b51ff..78c902866 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -467,7 +467,12 @@ void prep_lut(RTLIL::Design *design, int maxlut)
{
TimingInfo timing;
- std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
+ struct t_lut {
+ IdString name;
+ int area;
+ std::vector<int> delays;
+ };
+ std::map<int,t_lut> table;
for (auto module : design->modules()) {
auto it = module->attributes.find(ID::abc9_lut);
if (it == module->attributes.end())
@@ -476,40 +481,52 @@ void prep_lut(RTLIL::Design *design, int maxlut)
auto &t = timing.setup_module(module);
TimingInfo::NameBit o;
- std::vector<int> specify;
+ std::vector<int> delays;
for (const auto &i : t.comb) {
auto &d = i.first.second;
if (o == TimingInfo::NameBit())
o = d;
else if (o != d)
- log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module));
- specify.push_back(i.second);
+ log_error("Module '%s' with (* abc9_lut *) has more than one output.\n", log_id(module));
+ delays.push_back(i.second);
}
- if (maxlut && GetSize(specify) > maxlut)
+ if (GetSize(delays) == 0)
+ log_error("Module '%s' with (* abc9_lut *) has no specify entries.\n", log_id(module));
+ if (maxlut && GetSize(delays) > maxlut)
continue;
// ABC requires non-decreasing LUT input delays
- std::sort(specify.begin(), specify.end());
- table.emplace_back(GetSize(specify), module->name, it->second.as_int(), std::move(specify));
+ std::sort(delays.begin(), delays.end());
+
+ int K = GetSize(delays);
+ auto entry = t_lut{module->name, it->second.as_int(), std::move(delays)};
+ auto r = table.emplace(K, entry);
+ if (!r.second) {
+ if (r.first->second.area != entry.area)
+ log_error("Modules '%s' and '%s' have conflicting (* abc9_lut *) values.\n", log_id(module), log_id(r.first->second.name));
+ if (r.first->second.delays != entry.delays)
+ log_error("Modules '%s' and '%s' have conflicting specify entries.\n", log_id(module), log_id(r.first->second.name));
+ }
}
- // ABC requires ascending size
- std::sort(table.begin(), table.end());
+
+ if (table.empty())
+ log_error("Design does not contain any modules with (* abc9_lut *).\n");
std::stringstream ss;
- const auto &first = table.front();
+ const auto &front = *table.begin();
// If the first entry does not start from a 1-input LUT,
// (as ABC requires) crop the first entry to do so
- for (int i = 1; i < std::get<0>(first); i++) {
+ for (int i = 1; i < front.first; i++) {
ss << "# $__ABC9_LUT" << i << std::endl;
- ss << i << " " << std::get<2>(first);
+ ss << i << " " << front.second.area;
for (int j = 0; j < i; j++)
- ss << " " << std::get<3>(first)[j];
+ ss << " " << front.second.delays[j];
ss << std::endl;
}
for (const auto &i : table) {
- ss << "# " << log_id(std::get<1>(i)) << std::endl;
- ss << std::get<0>(i) << " " << std::get<2>(i);
- for (const auto &j : std::get<3>(i))
+ ss << "# " << log_id(i.second.name) << std::endl;
+ ss << i.first << " " << i.second.area;
+ for (const auto &j : i.second.delays)
ss << " " << j;
ss << std::endl;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-10 18:12:16 +0000