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-rw-r--r--passes/opt/opt_clean.cc6
-rw-r--r--passes/techmap/abc9.cc13
-rw-r--r--passes/techmap/muxcover.cc52
3 files changed, 44 insertions, 27 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index cfb0f788a..a8a8e0bc7 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -326,8 +326,8 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) {
// do not delete anything with "keep" or module ports or initialized wires
} else
- if (!purge_mode && check_public_name(wire->name)) {
- // do not get rid of public names unless in purge mode
+ if (!purge_mode && check_public_name(wire->name) && (raw_used_signals.check_any(s1) || used_signals.check_any(s2) || s1 != s2)) {
+ // do not get rid of public names unless in purge mode or if the wire is entirely unused, not even aliased
} else
if (!raw_used_signals.check_any(s1)) {
// delete wires that aren't used by anything directly
@@ -480,7 +480,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells())
- if (cell->type.in("$pos", "$_BUF_")) {
+ if (cell->type.in("$pos", "$_BUF_") && !cell->has_keep_attr()) {
bool is_signed = cell->type == "$pos" && cell->getParam("\\A_SIGNED").as_bool();
RTLIL::SigSpec a = cell->getPort("\\A");
RTLIL::SigSpec y = cell->getPort("\\Y");
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index b4f15d6a1..dbdd775f8 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -555,16 +555,15 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
vector<RTLIL::Cell*> boxes;
- for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
- RTLIL::Cell* cell = it->second;
+ for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) {
+ RTLIL::Cell *cell = it->second;
if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) {
- it = module->remove(it);
+ module->remove(cell);
continue;
}
RTLIL::Module* box_module = design->module(cell->type);
if (box_module && box_module->attributes.count("\\abc_box_id"))
- boxes.emplace_back(it->second);
- ++it;
+ boxes.emplace_back(cell);
}
std::map<std::string, int> cell_stats;
@@ -670,8 +669,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
}
- for (auto cell : boxes)
- module->remove(cell);
+ for (auto cell : boxes)
+ module->remove(cell);
// Copy connections (and rename) from mapped_mod to module
for (auto conn : mapped_mod->connections()) {
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index b0722134e..5642aeafc 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -330,13 +330,15 @@ struct MuxcoverWorker
ok = ok && follow_muxtree(S4, tree, bit, "BBS");
if (nodecode)
- ok = ok && S1 == S2 && S2 == S3 && S3 == S4;
+ ok = ok && (S1 == S2 || S1 == State::Sx || S2 == State::Sx) &&
+ /*S2 == S3 && */
+ (S3 == S4 || S3 == State::Sx || S4 == State::Sx);
ok = ok && follow_muxtree(T1, tree, bit, "AS");
ok = ok && follow_muxtree(T2, tree, bit, "BS");
if (nodecode)
- ok = ok && T1 == T2;
+ ok = ok && (T1 == T2 || T1 == State::Sx || T2 == State::Sx);
ok = ok && follow_muxtree(U1, tree, bit, "S");
@@ -353,11 +355,12 @@ struct MuxcoverWorker
mux.inputs.push_back(G);
mux.inputs.push_back(H);
+ mux.cost += prepare_decode_mux(T1, T2, U1, bit);
+
mux.cost += prepare_decode_mux(S1, S2, T1, bit);
mux.cost += prepare_decode_mux(S3, S4, T2, bit);
- mux.cost += prepare_decode_mux(S1, S3, U1, bit);
-
- mux.cost += prepare_decode_mux(T1, T2, U1, bit);
+ if (T1 != T2 && T1 != State::Sx && T2 != State::Sx)
+ mux.cost += prepare_decode_mux(S1, S3, U1, bit);
mux.selects.push_back(S1);
mux.selects.push_back(T1);
@@ -407,7 +410,13 @@ struct MuxcoverWorker
ok = ok && follow_muxtree(S8, tree, bit, "BBBS");
if (nodecode)
- ok = ok && S1 == S2 && S2 == S3 && S3 == S4 && S4 == S5 && S5 == S6 && S6 == S7 && S7 == S8;
+ ok = ok && (S1 == S2 || S1 == State::Sx || S2 == State::Sx) &&
+ /*S2 == S3 &&*/
+ (S3 == S4 || S3 == State::Sx || S4 == State::Sx) &&
+ /*S4 == S5 &&*/
+ (S5 == S6 || S5 == State::Sx || S6 == State::Sx) &&
+ /*S6 == S7 &&*/
+ (S7 == S8 || S7 == State::Sx || S8 == State::Sx);
ok = ok && follow_muxtree(T1, tree, bit, "AAS");
ok = ok && follow_muxtree(T2, tree, bit, "ABS");
@@ -415,13 +424,15 @@ struct MuxcoverWorker
ok = ok && follow_muxtree(T4, tree, bit, "BBS");
if (nodecode)
- ok = ok && T1 == T2 && T2 == T3 && T3 == T4;
+ ok = ok && (T1 == T2 || T1 == State::Sx || T2 == State::Sx) &&
+ /*T2 == T3 &&*/
+ (T3 == T4 || T3 == State::Sx || T4 == State::Sx);
ok = ok && follow_muxtree(U1, tree, bit, "AS");
ok = ok && follow_muxtree(U2, tree, bit, "BS");
if (nodecode)
- ok = ok && U1 == U2;
+ ok = ok && (U1 == U2 || U1 == State::Sx || U2 == State::Sx);
ok = ok && follow_muxtree(V1, tree, bit, "S");
@@ -446,19 +457,26 @@ struct MuxcoverWorker
mux.inputs.push_back(O);
mux.inputs.push_back(P);
- mux.cost += prepare_decode_mux(S1, S2, T1, bit);
- mux.cost += prepare_decode_mux(S3, S4, T2, bit);
- mux.cost += prepare_decode_mux(S5, S6, T3, bit);
- mux.cost += prepare_decode_mux(S7, S8, T4, bit);
- mux.cost += prepare_decode_mux(S1, S3, U1, bit);
- mux.cost += prepare_decode_mux(S5, S7, U2, bit);
- mux.cost += prepare_decode_mux(S1, S5, V1, bit);
+ mux.cost += prepare_decode_mux(U1, U2, V1, bit);
mux.cost += prepare_decode_mux(T1, T2, U1, bit);
mux.cost += prepare_decode_mux(T3, T4, U2, bit);
- mux.cost += prepare_decode_mux(T1, T3, V1, bit);
+ if (U1 != U2 && U1 != State::Sx && U2 != State::Sx) {
+ mux.cost += prepare_decode_mux(T1, T3, V1, bit);
- mux.cost += prepare_decode_mux(U1, U2, V1, bit);
+ mux.cost += prepare_decode_mux(S1, S2, T1, bit);
+ mux.cost += prepare_decode_mux(S3, S4, T2, bit);
+ if (T1 != T2 && T1 != State::Sx && T2 != State::Sx)
+ mux.cost += prepare_decode_mux(S1, S3, U1, bit);
+
+ mux.cost += prepare_decode_mux(S5, S6, T3, bit);
+ mux.cost += prepare_decode_mux(S7, S8, T4, bit);
+ if (T3 != T4 && T3 != State::Sx && T4 != State::Sx)
+ mux.cost += prepare_decode_mux(S5, S7, U2, bit);
+
+ if (T1 != T3 && T1 != State::Sx && T3 != State::Sx)
+ mux.cost += prepare_decode_mux(S1, S5, V1, bit);
+ }
mux.selects.push_back(S1);
mux.selects.push_back(T1);
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 04:36:56 +0000