2 files changed, 28 insertions, 13 deletions

diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 70d98713c..369fcc84e 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -184,9 +184,6 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
 	mem->parameters["\\OFFSET"] = Const(memory->start_offset);
 	mem->parameters["\\SIZE"] = Const(memory->size);
 	mem->parameters["\\ABITS"] = Const(addr_bits);
-
-	while (GetSize(init_data) > 1 && init_data.bits.back() == State::Sx && init_data.bits[GetSize(init_data)-2] == State::Sx)
-		init_data.bits.pop_back();
 	mem->parameters["\\INIT"] = init_data;
 
 	log_assert(sig_wr_clk.size() == wr_ports);
diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index b9e43d1db..3919e4b9c 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -77,18 +77,36 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
 	}
 	else
 	{
-		bool all_cases_are_empty = true;
-		for (auto cs : sw->cases) {
-			if (cs->actions.size() != 0 || cs->switches.size() != 0)
-				all_cases_are_empty = false;
+		bool all_fully_def = true;
+		for (auto cs : sw->cases)
+		{
 			if (max_depth != 0)
 				proc_clean_case(cs, did_something, count, max_depth-1);
+			for (auto cmp : cs->compare)
+				if (!cmp.is_fully_def())
+					all_fully_def = false;
 		}
-		if (all_cases_are_empty) {
-			did_something = true;
-			for (auto cs : sw->cases)
-				delete cs;
-			sw->cases.clear();
+		if (all_fully_def)
+		{
+			for (auto cs = sw->cases.begin(); cs != sw->cases.end();)
+			{
+				if ((*cs)->empty())
+				{
+					did_something = true;
+					delete *cs;
+					cs = sw->cases.erase(cs);
+				}
+				else ++cs;
+			}
+		}
+		else
+		{
+			while (!sw->cases.empty() && sw->cases.back()->empty())
+			{
+				did_something = true;
+				delete sw->cases.back();
+				sw->cases.pop_back();
+			}
 		}
 	}
 }
@@ -106,7 +124,7 @@ void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int m
 	}
 	for (size_t i = 0; i < cs->switches.size(); i++) {
 		RTLIL::SwitchRule *sw = cs->switches[i];
-		if (sw->cases.size() == 0) {
+		if (sw->empty()) {
 			cs->switches.erase(cs->switches.begin() + (i--));
 			did_something = true;
 			delete sw;