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-rw-r--r--passes/opt/wreduce.cc2
-rw-r--r--passes/proc/Makefile.inc2
-rw-r--r--passes/proc/proc.cc2
-rw-r--r--passes/proc/proc_arst.cc2
-rw-r--r--passes/proc/proc_init.cc26
-rw-r--r--passes/proc/proc_mux.cc26
-rw-r--r--passes/proc/proc_prune.cc158
-rw-r--r--passes/techmap/muxcover.cc27
8 files changed, 204 insertions, 41 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 1fbc41082..f749c8249 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -497,7 +497,7 @@ struct WreducePass : public Pass {
log(" flows that use the 'memory_memx' pass.\n");
log("\n");
log(" -keepdc\n");
- log(" Do not optimize explicit don't-care values.\n");
+ log(" Do not optimize explicit don't-care values on $mux cells.\n");
log("\n");
}
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
diff --git a/passes/proc/Makefile.inc b/passes/proc/Makefile.inc
index 397fe46a1..4b56979f8 100644
--- a/passes/proc/Makefile.inc
+++ b/passes/proc/Makefile.inc
@@ -1,5 +1,6 @@
OBJS += passes/proc/proc.o
+OBJS += passes/proc/proc_prune.o
OBJS += passes/proc/proc_clean.o
OBJS += passes/proc/proc_rmdead.o
OBJS += passes/proc/proc_init.o
@@ -7,4 +8,3 @@ OBJS += passes/proc/proc_arst.o
OBJS += passes/proc/proc_mux.o
OBJS += passes/proc/proc_dlatch.o
OBJS += passes/proc/proc_dff.o
-
diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc
index ef7cb0f71..a5b4a3112 100644
--- a/passes/proc/proc.cc
+++ b/passes/proc/proc.cc
@@ -37,6 +37,7 @@ struct ProcPass : public Pass {
log("\n");
log(" proc_clean\n");
log(" proc_rmdead\n");
+ log(" proc_prune\n");
log(" proc_init\n");
log(" proc_arst\n");
log(" proc_mux\n");
@@ -83,6 +84,7 @@ struct ProcPass : public Pass {
Pass::call(design, "proc_clean");
if (!ifxmode)
Pass::call(design, "proc_rmdead");
+ Pass::call(design, "proc_prune");
Pass::call(design, "proc_init");
if (global_arst.empty())
Pass::call(design, "proc_arst");
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index b69eba3f9..d069f152a 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -172,7 +172,7 @@ restart_proc_arst:
sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0;
}
for (auto &action : sync->actions) {
- RTLIL::SigSpec rspec = action.second;
+ RTLIL::SigSpec rspec = assign_map(action.second);
RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size());
for (int i = 0; i < GetSize(rspec); i++)
if (rspec[i].wire == NULL)
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index e2dc07e53..462a384b7 100644
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -26,21 +26,7 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule)
-{
- log_assert(rule.compare.size() == 0);
-
- while (1) {
- RTLIL::SigSpec tmp = sig;
- for (auto &it : rule.actions)
- tmp.replace(it.first, it.second);
- if (tmp == sig)
- break;
- sig = tmp;
- }
-}
-
-void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
+void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
{
bool found_init = false;
@@ -53,9 +39,7 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
for (auto &action : sync->actions)
{
RTLIL::SigSpec lhs = action.first;
- RTLIL::SigSpec rhs = action.second;
-
- proc_get_const(rhs, proc->root_case);
+ RTLIL::SigSpec rhs = sigmap(action.second);
if (!rhs.is_fully_const())
log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
@@ -120,10 +104,12 @@ struct ProcInitPass : public Pass {
extra_args(args, 1, design);
for (auto mod : design->modules())
- if (design->selected(mod))
+ if (design->selected(mod)) {
+ SigMap sigmap(mod);
for (auto &proc_it : mod->processes)
if (design->selected(mod, proc_it.second))
- proc_init(mod, proc_it.second);
+ proc_init(mod, sigmap, proc_it.second);
+ }
}
} ProcInitPass;
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index aac0b121c..d029282fd 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -144,7 +144,13 @@ struct SnippetSwCache
}
};
-RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, bool ifxmode)
+void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs)
+{
+ cell->attributes = sw->attributes;
+ cell->add_strpool_attribute("\\src", cs->get_strpool_attribute("\\src"));
+}
+
+RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
{
std::stringstream sstr;
sstr << "$procmux$" << (autoidx++);
@@ -173,7 +179,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
{
// create compare cell
RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? "$eqx" : "$eq");
- eq_cell->attributes = sw->attributes;
+ apply_attrs(eq_cell, sw, cs);
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0);
@@ -199,7 +205,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
// reduce cmp vector to one logic signal
RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or");
- any_cell->attributes = sw->attributes;
+ apply_attrs(any_cell, sw, cs);
any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
@@ -212,7 +218,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
return RTLIL::SigSpec(ctrl_wire);
}
-RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, bool ifxmode)
+RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
{
log_assert(when_signal.size() == else_signal.size());
@@ -224,7 +230,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
return when_signal;
// compare results
- RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, ifxmode);
+ RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
if (ctrl_sig.size() == 0)
return when_signal;
log_assert(ctrl_sig.size() == 1);
@@ -234,7 +240,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
// create the multiplexer itself
RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux");
- mux_cell->attributes = sw->attributes;
+ apply_attrs(mux_cell, sw, cs);
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
mux_cell->setPort("\\A", else_signal);
@@ -246,7 +252,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
return RTLIL::SigSpec(result_wire);
}
-void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, bool ifxmode)
+void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
{
log_assert(last_mux_cell != NULL);
log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size());
@@ -254,7 +260,7 @@ void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::ve
if (when_signal == last_mux_cell->getPort("\\A"))
return;
- RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, ifxmode);
+ RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
log_assert(ctrl_sig.size() == 1);
last_mux_cell->type = "$pmux";
@@ -395,9 +401,9 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
RTLIL::CaseRule *cs2 = sw->cases[case_idx];
RTLIL::SigSpec value = signal_to_mux_tree(mod, swcache, swpara, cs2, sig, initial_val, ifxmode);
if (last_mux_cell && pgroups[case_idx] == pgroups[case_idx+1])
- append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw, ifxmode);
+ append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw, cs2, ifxmode);
else
- result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw, ifxmode);
+ result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw, cs2, ifxmode);
}
}
diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc
new file mode 100644
index 000000000..9e00b0a8a
--- /dev/null
+++ b/passes/proc/proc_prune.cc
@@ -0,0 +1,158 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2019 whitequark <whitequark@whitequark.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/sigtools.h"
+#include "kernel/log.h"
+#include <stdlib.h>
+#include <stdio.h>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct PruneWorker
+{
+ RTLIL::Module *module;
+ SigMap sigmap;
+
+ int removed_count = 0, promoted_count = 0;
+
+ PruneWorker(RTLIL::Module *mod) : module(mod), sigmap(mod) {}
+
+ pool<RTLIL::SigBit> do_switch(RTLIL::SwitchRule *sw, pool<RTLIL::SigBit> assigned, pool<RTLIL::SigBit> &affected)
+ {
+ pool<RTLIL::SigBit> all_assigned;
+ bool full_case = sw->get_bool_attribute("\\full_case");
+ bool first = true;
+ for (auto it : sw->cases) {
+ if (it->compare.empty())
+ full_case = true;
+ pool<RTLIL::SigBit> case_assigned = do_case(it, assigned, affected);
+ if (first) {
+ first = false;
+ all_assigned = case_assigned;
+ } else {
+ for (auto &bit : all_assigned)
+ if (!case_assigned[bit])
+ all_assigned.erase(bit);
+ }
+ }
+ if (full_case)
+ assigned.insert(all_assigned.begin(), all_assigned.end());
+ return assigned;
+ }
+
+ pool<RTLIL::SigBit> do_case(RTLIL::CaseRule *cs, pool<RTLIL::SigBit> assigned, pool<RTLIL::SigBit> &affected,
+ bool root = false)
+ {
+ for (auto it = cs->switches.rbegin(); it != cs->switches.rend(); ++it) {
+ pool<RTLIL::SigBit> sw_assigned = do_switch((*it), assigned, affected);
+ assigned.insert(sw_assigned.begin(), sw_assigned.end());
+ }
+ pool<RTLIL::SigSig> remove;
+ for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ++it) {
+ RTLIL::SigSpec lhs = sigmap(it->first);
+ bool redundant = true;
+ for (auto &bit : lhs) {
+ if (bit.wire && !assigned[bit]) {
+ redundant = false;
+ break;
+ }
+ }
+ if (redundant) {
+ removed_count++;
+ remove.insert(*it);
+ } else {
+ if (root) {
+ bool promotable = true;
+ for (auto &bit : lhs) {
+ if (bit.wire && affected[bit]) {
+ promotable = false;
+ break;
+ }
+ }
+ if (promotable) {
+ promoted_count++;
+ module->connect(*it);
+ remove.insert(*it);
+ }
+ }
+ for (auto &bit : lhs)
+ if (bit.wire)
+ assigned.insert(bit);
+ for (auto &bit : lhs)
+ if (bit.wire)
+ affected.insert(bit);
+ }
+ }
+ for (auto it = cs->actions.begin(); it != cs->actions.end(); ) {
+ if (remove[*it]) {
+ it = cs->actions.erase(it);
+ } else it++;
+ }
+ return assigned;
+ }
+
+ void do_process(RTLIL::Process *pr)
+ {
+ pool<RTLIL::SigBit> affected;
+ do_case(&pr->root_case, {}, affected, /*root=*/true);
+ }
+};
+
+struct ProcPrunePass : public Pass {
+ ProcPrunePass() : Pass("proc_prune", "remove redundant assignments") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" proc_prune [selection]\n");
+ log("\n");
+ log("This pass identifies assignments in processes that are always overwritten by\n");
+ log("a later assignment to the same signal and removes them.\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ int total_removed_count = 0, total_promoted_count = 0;
+ log_header(design, "Executing PROC_PRUNE pass (remove redundant assignments in processes).\n");
+
+ extra_args(args, 1, design);
+
+ for (auto mod : design->modules()) {
+ if (!design->selected(mod))
+ continue;
+ PruneWorker worker(mod);
+ for (auto &proc_it : mod->processes) {
+ if (!design->selected(mod, proc_it.second))
+ continue;
+ worker.do_process(proc_it.second);
+ }
+ total_removed_count += worker.removed_count;
+ total_promoted_count += worker.promoted_count;
+ }
+
+ log("Removed %d redundant assignment%s.\n",
+ total_removed_count, total_removed_count == 1 ? "" : "s");
+ log("Promoted %d assignment%s to connection%s.\n",
+ total_promoted_count, total_promoted_count == 1 ? "" : "s", total_promoted_count == 1 ? "" : "s");
+ }
+} ProcPrunePass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index c84cfc39a..d53378a29 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -632,10 +632,15 @@ struct MuxcoverPass : public Pass {
log("Cover trees of $_MUX_ cells with $_MUX{4,8,16}_ cells\n");
log("\n");
log(" -mux4[=cost], -mux8[=cost], -mux16[=cost]\n");
- log(" Use the specified types of MUXes (with optional integer costs). If none\n");
- log(" of these options are given, the effect is the same as if all of them are.\n");
- log(" Default costs: $_MUX_ = %d, $_MUX4_ = %d,\n", COST_MUX2, COST_MUX4);
- log(" $_MUX8_ = %d, $_MUX16_ = %d\n", COST_MUX8, COST_MUX16);
+ log(" Cover $_MUX_ trees using the specified types of MUXes (with optional\n");
+ log(" integer costs). If none of these options are given, the effect is the\n");
+ log(" same as if all of them are.\n");
+ log(" Default costs: $_MUX4_ = %d, $_MUX8_ = %d, \n", COST_MUX4, COST_MUX8);
+ log(" $_MUX16_ = %d\n", COST_MUX16);
+ log("\n");
+ log(" -mux2=cost\n");
+ log(" Use the specified cost for $_MUX_ cells when making covering decisions.\n");
+ log(" Default cost: $_MUX_ = %d\n", COST_MUX2);
log("\n");
log(" -dmux=cost\n");
log(" Use the specified cost for $_MUX_ cells used in decoders.\n");
@@ -661,6 +666,7 @@ struct MuxcoverPass : public Pass {
bool nodecode = false;
bool nopartial = false;
int cost_dmux = COST_DMUX;
+ int cost_mux2 = COST_MUX2;
int cost_mux4 = COST_MUX4;
int cost_mux8 = COST_MUX8;
int cost_mux16 = COST_MUX16;
@@ -669,11 +675,15 @@ struct MuxcoverPass : public Pass {
for (argidx = 1; argidx < args.size(); argidx++)
{
const auto &arg = args[argidx];
+ if (arg.size() >= 6 && arg.substr(0,6) == "-mux2=") {
+ cost_mux2 = std::stoi(arg.substr(6));
+ continue;
+ }
if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") {
use_mux4 = true;
if (arg.size() > 5) {
if (arg[5] != '=') break;
- cost_mux4 = atoi(arg.substr(6).c_str());
+ cost_mux4 = std::stoi(arg.substr(6));
}
continue;
}
@@ -681,7 +691,7 @@ struct MuxcoverPass : public Pass {
use_mux8 = true;
if (arg.size() > 5) {
if (arg[5] != '=') break;
- cost_mux8 = atoi(arg.substr(6).c_str());
+ cost_mux8 = std::stoi(arg.substr(6));
}
continue;
}
@@ -689,12 +699,12 @@ struct MuxcoverPass : public Pass {
use_mux16 = true;
if (arg.size() > 6) {
if (arg[6] != '=') break;
- cost_mux16 = atoi(arg.substr(7).c_str());
+ cost_mux16 = std::stoi(arg.substr(7));
}
continue;
}
if (arg.size() >= 6 && arg.substr(0,6) == "-dmux=") {
- cost_dmux = atoi(arg.substr(6).c_str());
+ cost_dmux = std::stoi(arg.substr(6));
continue;
}
if (arg == "-nodecode") {
@@ -722,6 +732,7 @@ struct MuxcoverPass : public Pass {
worker.use_mux8 = use_mux8;
worker.use_mux16 = use_mux16;
worker.cost_dmux = cost_dmux;
+ worker.cost_mux2 = cost_mux2;
worker.cost_mux4 = cost_mux4;
worker.cost_mux8 = cost_mux8;
worker.cost_mux16 = cost_mux16;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-13 04:39:34 +0000