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-rw-r--r--passes/opt/opt_merge.cc234
-rw-r--r--passes/sat/expose.cc151
2 files changed, 168 insertions, 217 deletions
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 8823a9061..4aa78ff39 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -26,7 +26,6 @@
#include <stdio.h>
#include <set>
-#define USE_CELL_HASH_CACHE
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@@ -41,9 +40,7 @@ struct OptMergeWorker
CellTypes ct;
int total_count;
-#ifdef USE_CELL_HASH_CACHE
- dict<const RTLIL::Cell*, std::string> cell_hash_cache;
-#endif
+ SHA1 checksum;
static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
{
@@ -68,7 +65,6 @@ struct OptMergeWorker
}
}
-#ifdef USE_CELL_HASH_CACHE
std::string int_to_hash_string(unsigned int v)
{
if (v == 0)
@@ -83,14 +79,9 @@ struct OptMergeWorker
std::string hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
{
- if (cell_hash_cache.count(cell) > 0)
- return cell_hash_cache[cell];
-
+ vector<string> hash_conn_strings;
std::string hash_string = cell->type.str() + "\n";
- for (auto &it : cell->parameters)
- hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n";
-
const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
@@ -124,13 +115,22 @@ struct OptMergeWorker
conn = &alt_conn;
}
- vector<string> hash_conn_strings;
-
for (auto &it : *conn) {
- if (cell->output(it.first))
- continue;
- RTLIL::SigSpec sig = it.second;
- assign_map.apply(sig);
+ RTLIL::SigSpec sig;
+ if (cell->output(it.first)) {
+ if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
+ cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
+ cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
+ // For the 'Q' output of state elements,
+ // use its (* init *) attribute value
+ for (const auto &b : dff_init_map(it.second))
+ sig.append(b.wire ? State::Sx : b);
+ }
+ else
+ continue;
+ }
+ else
+ sig = assign_map(it.second);
string s = "C " + it.first.str() + "=";
for (auto &chunk : sig.chunks()) {
if (chunk.wire)
@@ -143,50 +143,59 @@ struct OptMergeWorker
hash_conn_strings.push_back(s + "\n");
}
+ for (auto &it : cell->parameters)
+ hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
+
std::sort(hash_conn_strings.begin(), hash_conn_strings.end());
for (auto it : hash_conn_strings)
hash_string += it;
- cell_hash_cache[cell] = sha1(hash_string);
- return cell_hash_cache[cell];
+ checksum.update(hash_string);
+ return checksum.final();
}
-#endif
- bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2, bool &lt)
+ bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
{
-#ifdef USE_CELL_HASH_CACHE
- std::string hash1 = hash_cell_parameters_and_connections(cell1);
- std::string hash2 = hash_cell_parameters_and_connections(cell2);
-
- if (hash1 != hash2) {
- lt = hash1 < hash2;
- return true;
- }
-#endif
-
- if (cell1->parameters != cell2->parameters) {
- std::map<RTLIL::IdString, RTLIL::Const> p1(cell1->parameters.begin(), cell1->parameters.end());
- std::map<RTLIL::IdString, RTLIL::Const> p2(cell2->parameters.begin(), cell2->parameters.end());
- lt = p1 < p2;
- return true;
- }
-
- dict<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections();
- dict<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
-
- for (auto &it : conn1) {
- if (cell1->output(it.first))
- it.second = RTLIL::SigSpec();
- else
- assign_map.apply(it.second);
- }
-
- for (auto &it : conn2) {
- if (cell2->output(it.first))
- it.second = RTLIL::SigSpec();
- else
- assign_map.apply(it.second);
+ log_assert(cell1 != cell2);
+ if (cell1->type != cell2->type) return false;
+
+ if (cell1->parameters != cell2->parameters)
+ return false;
+
+ if (cell1->connections_.size() != cell2->connections_.size())
+ return false;
+ for (const auto &it : cell1->connections_)
+ if (!cell2->connections_.count(it.first))
+ return false;
+
+ decltype(Cell::connections_) conn1, conn2;
+ conn1.reserve(cell1->connections_.size());
+ conn2.reserve(cell1->connections_.size());
+
+ for (const auto &it : cell1->connections_) {
+ if (cell1->output(it.first)) {
+ if (it.first == ID(Q) && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
+ cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
+ cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
+ // For the 'Q' output of state elements,
+ // use the (* init *) attribute value
+ auto &sig1 = conn1[it.first];
+ for (const auto &b : dff_init_map(it.second))
+ sig1.append(b.wire ? State::Sx : b);
+ auto &sig2 = conn2[it.first];
+ for (const auto &b : dff_init_map(cell2->getPort(it.first)))
+ sig2.append(b.wire ? State::Sx : b);
+ }
+ else {
+ conn1[it.first] = RTLIL::SigSpec();
+ conn2[it.first] = RTLIL::SigSpec();
+ }
+ }
+ else {
+ conn1[it.first] = assign_map(it.second);
+ conn2[it.first] = assign_map(cell2->getPort(it.first));
+ }
}
if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) ||
@@ -215,54 +224,9 @@ struct OptMergeWorker
sort_pmux_conn(conn2);
}
- if (conn1 != conn2) {
- std::map<RTLIL::IdString, RTLIL::SigSpec> c1(conn1.begin(), conn1.end());
- std::map<RTLIL::IdString, RTLIL::SigSpec> c2(conn2.begin(), conn2.end());
- lt = c1 < c2;
- return true;
- }
-
- if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
- cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
- cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
- std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
- std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
- for (size_t i = 0; i < q1.size(); i++)
- if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
- lt = q1.at(i) < q2.at(i);
- return true;
- }
- }
-
- return false;
+ return conn1 == conn2;
}
- bool compare_cells(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
- {
- if (cell1->type != cell2->type)
- return cell1->type < cell2->type;
-
- if ((!mode_share_all && !ct.cell_known(cell1->type)) || !cell1->known())
- return cell1 < cell2;
-
- if (cell1->has_keep_attr() || cell2->has_keep_attr())
- return cell1 < cell2;
-
- bool lt;
- if (compare_cell_parameters_and_connections(cell1, cell2, lt))
- return lt;
-
- return false;
- }
-
- struct CompareCells {
- OptMergeWorker *that;
- CompareCells(OptMergeWorker *that) : that(that) {}
- bool operator()(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const {
- return that->compare_cells(cell1, cell2);
- }
- };
-
OptMergeWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) :
design(design), module(module), assign_map(module), mode_share_all(mode_share_all)
{
@@ -299,9 +263,6 @@ struct OptMergeWorker
bool did_something = true;
while (did_something)
{
-#ifdef USE_CELL_HASH_CACHE
- cell_hash_cache.clear();
-#endif
std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells_.size());
for (auto &it : module->cells_) {
@@ -312,42 +273,51 @@ struct OptMergeWorker
}
did_something = false;
- std::map<RTLIL::Cell*, RTLIL::Cell*, CompareCells> sharemap(CompareCells(this));
+ dict<std::string, RTLIL::Cell*> sharemap;
for (auto cell : cells)
{
- if (sharemap.count(cell) > 0) {
- did_something = true;
- log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
- for (auto &it : cell->connections()) {
- if (cell->output(it.first)) {
- RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first);
- log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
- log_signal(it.second), log_signal(other_sig));
- module->connect(RTLIL::SigSig(it.second, other_sig));
- assign_map.add(it.second, other_sig);
-
- if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
- cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
- cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
- for (auto c : it.second.chunks()) {
- auto jt = c.wire->attributes.find(ID(init));
- if (jt == c.wire->attributes.end())
- continue;
- for (int i = c.offset; i < c.offset + c.width; i++)
- jt->second[i] = State::Sx;
+ if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known())
+ continue;
+
+ auto hash = hash_cell_parameters_and_connections(cell);
+ auto r = sharemap.insert(std::make_pair(hash, cell));
+ if (!r.second) {
+ if (compare_cell_parameters_and_connections(cell, r.first->second)) {
+ if (cell->has_keep_attr()) {
+ if (r.first->second->has_keep_attr())
+ continue;
+ std::swap(r.first->second, cell);
+ }
+
+
+ did_something = true;
+ log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), r.first->second->name.c_str());
+ for (auto &it : cell->connections()) {
+ if (cell->output(it.first)) {
+ RTLIL::SigSpec other_sig = r.first->second->getPort(it.first);
+ log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
+ log_signal(it.second), log_signal(other_sig));
+ module->connect(RTLIL::SigSig(it.second, other_sig));
+ assign_map.add(it.second, other_sig);
+
+ if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
+ cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
+ cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
+ for (auto c : it.second.chunks()) {
+ auto jt = c.wire->attributes.find(ID(init));
+ if (jt == c.wire->attributes.end())
+ continue;
+ for (int i = c.offset; i < c.offset + c.width; i++)
+ jt->second[i] = State::Sx;
+ }
+ dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
}
- dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
}
}
+ log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
+ module->remove(cell);
+ total_count++;
}
- log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
-#ifdef USE_CELL_HASH_CACHE
- cell_hash_cache.erase(cell);
-#endif
- module->remove(cell);
- total_count++;
- } else {
- sharemap[cell] = cell;
}
}
}
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 29dfc7b19..8fb47f357 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -53,7 +53,7 @@ bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells,
{
if (cell->name[0] == '$' || dff_cells.count(cell->name))
return false;
- if (cell->type[0] == '\\' && !design->modules_.count(cell->type))
+ if (cell->type[0] == '\\' && (design->module(cell->type) == nullptr))
return false;
return true;
}
@@ -85,27 +85,24 @@ void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
SigMap sigmap(module);
SigPool dffsignals;
- for (auto &it : module->cells_) {
- if (ct.cell_known(it.second->type) && it.second->hasPort("\\Q"))
- dffsignals.add(sigmap(it.second->getPort("\\Q")));
+ for (auto cell : module->cells()) {
+ if (ct.cell_known(cell->type) && cell->hasPort("\\Q"))
+ dffsignals.add(sigmap(cell->getPort("\\Q")));
}
- for (auto &it : module->wires_) {
- if (dffsignals.check_any(it.second))
- dff_wires.insert(it.first);
+ for (auto w : module->wires()) {
+ if (dffsignals.check_any(w))
+ dff_wires.insert(w->name);
}
}
-void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module)
+void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Module *module)
{
std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info;
SigMap sigmap(module);
- for (auto &it : module->cells_)
+ for (auto cell : module->selected_cells())
{
- if (!design->selected(module, it.second))
- continue;
-
dff_map_bit_info_t info;
info.bit_d = RTLIL::State::Sm;
info.bit_clk = RTLIL::State::Sm;
@@ -113,7 +110,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
info.clk_polarity = false;
info.arst_polarity = false;
info.arst_value = RTLIL::State::Sm;
- info.cell = it.second;
+ info.cell = cell;
if (info.cell->type == "$dff") {
info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
@@ -164,12 +161,12 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
}
std::map<RTLIL::IdString, dff_map_info_t> empty_dq_map;
- for (auto &it : module->wires_)
+ for (auto w : module->wires())
{
- if (!consider_wire(it.second, empty_dq_map))
+ if (!consider_wire(w, empty_dq_map))
continue;
- std::vector<RTLIL::SigBit> bits_q = sigmap(it.second).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> bits_q = sigmap(w).to_sigbit_vector();
std::vector<RTLIL::SigBit> bits_d;
std::vector<RTLIL::State> arst_value;
std::set<RTLIL::Cell*> cells;
@@ -207,7 +204,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
info.arst_value = arst_value;
for (auto it : cells)
info.cells.push_back(it->name);
- map[it.first] = info;
+ map[w->name] = info;
}
}
@@ -314,26 +311,23 @@ struct ExposePass : public Pass {
RTLIL::Module *first_module = NULL;
std::set<RTLIL::IdString> shared_dff_wires;
- for (auto &mod_it : design->modules_)
+ for (auto mod : design->selected_modules())
{
- if (!design->selected(mod_it.second))
- continue;
-
- create_dff_dq_map(dff_dq_maps[mod_it.second], design, mod_it.second);
+ create_dff_dq_map(dff_dq_maps[mod], mod);
if (!flag_shared)
continue;
if (first_module == NULL) {
- for (auto &it : dff_dq_maps[mod_it.second])
+ for (auto &it : dff_dq_maps[mod])
shared_dff_wires.insert(it.first);
- first_module = mod_it.second;
+ first_module = mod;
} else {
std::set<RTLIL::IdString> new_shared_dff_wires;
for (auto &it : shared_dff_wires) {
- if (!dff_dq_maps[mod_it.second].count(it))
+ if (!dff_dq_maps[mod].count(it))
continue;
- if (!compare_wires(first_module->wires_.at(it), mod_it.second->wires_.at(it)))
+ if (!compare_wires(first_module->wire(it), mod->wire(it)))
continue;
new_shared_dff_wires.insert(it);
}
@@ -364,28 +358,23 @@ struct ExposePass : public Pass {
{
RTLIL::Module *first_module = NULL;
- for (auto &mod_it : design->modules_)
+ for (auto module : design->selected_modules())
{
- RTLIL::Module *module = mod_it.second;
-
- if (!design->selected(module))
- continue;
-
std::set<RTLIL::IdString> dff_wires;
if (flag_dff)
find_dff_wires(dff_wires, module);
if (first_module == NULL)
{
- for (auto &it : module->wires_)
- if (design->selected(module, it.second) && consider_wire(it.second, dff_dq_maps[module]))
- if (!flag_dff || dff_wires.count(it.first))
- shared_wires.insert(it.first);
+ for (auto w : module->wires())
+ if (design->selected(module, w) && consider_wire(w, dff_dq_maps[module]))
+ if (!flag_dff || dff_wires.count(w->name))
+ shared_wires.insert(w->name);
if (flag_evert)
- for (auto &it : module->cells_)
- if (design->selected(module, it.second) && consider_cell(design, dff_cells[module], it.second))
- shared_cells.insert(it.first);
+ for (auto cell : module->cells())
+ if (design->selected(module, cell) && consider_cell(design, dff_cells[module], cell))
+ shared_cells.insert(cell->name);
first_module = module;
}
@@ -397,16 +386,16 @@ struct ExposePass : public Pass {
{
RTLIL::Wire *wire;
- if (module->wires_.count(it) == 0)
+ if (module->wire(it) == nullptr)
goto delete_shared_wire;
- wire = module->wires_.at(it);
+ wire = module->wire(it);
if (!design->selected(module, wire))
goto delete_shared_wire;
if (!consider_wire(wire, dff_dq_maps[module]))
goto delete_shared_wire;
- if (!compare_wires(first_module->wires_.at(it), wire))
+ if (!compare_wires(first_module->wire(it), wire))
goto delete_shared_wire;
if (flag_dff && !dff_wires.count(it))
goto delete_shared_wire;
@@ -421,16 +410,16 @@ struct ExposePass : public Pass {
{
RTLIL::Cell *cell;
- if (module->cells_.count(it) == 0)
+ if (module->cell(it) == nullptr)
goto delete_shared_cell;
- cell = module->cells_.at(it);
+ cell = module->cell(it);
if (!design->selected(module, cell))
goto delete_shared_cell;
if (!consider_cell(design, dff_cells[module], cell))
goto delete_shared_cell;
- if (!compare_cells(first_module->cells_.at(it), cell))
+ if (!compare_cells(first_module->cell(it), cell))
goto delete_shared_cell;
if (0)
@@ -446,13 +435,8 @@ struct ExposePass : public Pass {
}
}
- for (auto &mod_it : design->modules_)
+ for (auto module : design->selected_modules())
{
- RTLIL::Module *module = mod_it.second;
-
- if (!design->selected(module))
- continue;
-
std::set<RTLIL::IdString> dff_wires;
if (flag_dff && !flag_shared)
find_dff_wires(dff_wires, module);
@@ -461,49 +445,49 @@ struct ExposePass : public Pass {
SigMap out_to_in_map;
- for (auto &it : module->wires_)
+ for (auto w : module->wires())
{
if (flag_shared) {
- if (shared_wires.count(it.first) == 0)
+ if (shared_wires.count(w->name) == 0)
continue;
} else {
- if (!design->selected(module, it.second) || !consider_wire(it.second, dff_dq_maps[module]))
+ if (!design->selected(module, w) || !consider_wire(w, dff_dq_maps[module]))
continue;
- if (flag_dff && !dff_wires.count(it.first))
+ if (flag_dff && !dff_wires.count(w->name))
continue;
}
if (flag_input)
{
- if (!it.second->port_input) {
- it.second->port_input = true;
- log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name));
- RTLIL::Wire *w = module->addWire(NEW_ID, GetSize(it.second));
- out_to_in_map.add(it.second, w);
+ if (!w->port_input) {
+ w->port_input = true;
+ log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
+ RTLIL::Wire *in_wire = module->addWire(NEW_ID, GetSize(w));
+ out_to_in_map.add(w, in_wire);
}
}
else
{
- if (!it.second->port_output) {
- it.second->port_output = true;
- log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name));
+ if (!w->port_output) {
+ w->port_output = true;
+ log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
}
if (flag_cut) {
- RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width);
+ RTLIL::Wire *in_wire = add_new_wire(module, w->name.str() + sep + "i", w->width);
in_wire->port_input = true;
- out_to_in_map.add(sigmap(it.second), in_wire);
+ out_to_in_map.add(sigmap(w), in_wire);
}
}
}
if (flag_input)
{
- for (auto &it : module->cells_) {
- if (!ct.cell_known(it.second->type))
+ for (auto cell : module->cells()) {
+ if (!ct.cell_known(cell->type))
continue;
- for (auto &conn : it.second->connections_)
- if (ct.cell_output(it.second->type, conn.first))
+ for (auto &conn : cell->connections_)
+ if (ct.cell_output(cell->type, conn.first))
conn.second = out_to_in_map(sigmap(conn.second));
}
@@ -513,11 +497,11 @@ struct ExposePass : public Pass {
if (flag_cut)
{
- for (auto &it : module->cells_) {
- if (!ct.cell_known(it.second->type))
+ for (auto cell : module->cells()) {
+ if (!ct.cell_known(cell->type))
continue;
- for (auto &conn : it.second->connections_)
- if (ct.cell_input(it.second->type, conn.first))
+ for (auto &conn : cell->connections_)
+ if (ct.cell_input(cell->type, conn.first))
conn.second = out_to_in_map(sigmap(conn.second));
}
@@ -529,10 +513,10 @@ struct ExposePass : public Pass {
for (auto &dq : dff_dq_maps[module])
{
- if (!module->wires_.count(dq.first))
+ if (module->wire(dq.first) == nullptr)
continue;
- RTLIL::Wire *wire = module->wires_.at(dq.first);
+ RTLIL::Wire *wire = module->wire(dq.first);
std::set<RTLIL::SigBit> wire_bits_set = sigmap(wire).to_sigbit_set();
std::vector<RTLIL::SigBit> wire_bits_vec = sigmap(wire).to_sigbit_vector();
@@ -541,7 +525,7 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0);
for (auto &cell_name : info.cells) {
- RTLIL::Cell *cell = module->cells_.at(cell_name);
+ RTLIL::Cell *cell = module->cell(cell_name);
std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort("\\Q")).to_sigbit_vector();
for (auto &bit : cell_q_bits)
if (wire_bits_set.count(bit))
@@ -609,25 +593,22 @@ struct ExposePass : public Pass {
{
std::vector<RTLIL::Cell*> delete_cells;
- for (auto &it : module->cells_)
+ for (auto cell : module->cells())
{
if (flag_shared) {
- if (shared_cells.count(it.first) == 0)
+ if (shared_cells.count(cell->name) == 0)
continue;
} else {
- if (!design->selected(module, it.second) || !consider_cell(design, dff_cells[module], it.second))
+ if (!design->selected(module, cell) || !consider_cell(design, dff_cells[module], cell))
continue;
}
- RTLIL::Cell *cell = it.second;
-
- if (design->modules_.count(cell->type))
+ if (design->module(cell->type) != nullptr)
{
- RTLIL::Module *mod = design->modules_.at(cell->type);
+ RTLIL::Module *mod = design->module(cell->type);
- for (auto &it : mod->wires_)
+ for (auto p : mod->wires())
{
- RTLIL::Wire *p = it.second;
if (!p->port_input && !p->port_output)
continue;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-16 01:52:04 +0000