diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/rename.cc | 50 | ||||
| -rw-r--r-- | passes/cmds/select.cc | 58 | ||||
| -rw-r--r-- | passes/equiv/Makefile.inc | 2 | ||||
| -rw-r--r-- | passes/equiv/equiv_make.cc | 86 | ||||
| -rw-r--r-- | passes/equiv/equiv_opt.cc | 157 | ||||
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 229 | ||||
| -rw-r--r-- | passes/memory/memory_bram.cc | 18 | ||||
| -rw-r--r-- | passes/memory/memory_dff.cc | 2 | ||||
| -rw-r--r-- | passes/opt/Makefile.inc | 1 | ||||
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 | ||||
| -rw-r--r-- | passes/opt/opt_lut.cc | 503 | ||||
| -rw-r--r-- | passes/opt/opt_muxtree.cc | 18 | ||||
| -rw-r--r-- | passes/techmap/deminout.cc | 7 | ||||
| -rw-r--r-- | passes/techmap/dff2dffe.cc | 35 | ||||
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 12 | ||||
| -rw-r--r-- | passes/techmap/libparse.cc | 15 | ||||
| -rw-r--r-- | passes/techmap/lut2mux.cc | 2 |
17 files changed, 1163 insertions, 34 deletions
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index dce576fdf..4b4af0a40 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -52,6 +52,15 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: log_cmd_error("Object `%s' not found!\n", from_name.c_str()); } +static std::string derive_name_from_src(const std::string &src, int counter) +{ + std::string src_base = src.substr(0, src.find('|')); + if (src_base.empty()) + return stringf("$%d", counter); + else + return stringf("\\%s$%d", src_base.c_str(), counter); +} + struct RenamePass : public Pass { RenamePass() : Pass("rename", "rename object in the design") { } void help() YS_OVERRIDE @@ -63,6 +72,10 @@ struct RenamePass : public Pass { log("Rename the specified object. Note that selection patterns are not supported\n"); log("by this command.\n"); log("\n"); + log(" rename -src [selection]\n"); + log("\n"); + log("Assign names auto-generated from the src attribute to all selected wires and\n"); + log("cells with private names.\n"); log("\n"); log(" rename -enumerate [-pattern <pattern>] [selection]\n"); log("\n"); @@ -84,6 +97,7 @@ struct RenamePass : public Pass { void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { std::string pattern_prefix = "_", pattern_suffix = "_"; + bool flag_src = false; bool flag_enumerate = false; bool flag_hide = false; bool flag_top = false; @@ -93,6 +107,11 @@ struct RenamePass : public Pass { for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; + if (arg == "-src" && !got_mode) { + flag_src = true; + got_mode = true; + continue; + } if (arg == "-enumerate" && !got_mode) { flag_enumerate = true; got_mode = true; @@ -117,6 +136,37 @@ struct RenamePass : public Pass { break; } + if (flag_src) + { + extra_args(args, argidx, design); + + for (auto &mod : design->modules_) + { + int counter = 0; + + RTLIL::Module *module = mod.second; + if (!design->selected(module)) + continue; + + dict<RTLIL::IdString, RTLIL::Wire*> new_wires; + for (auto &it : module->wires_) { + if (it.first[0] == '$' && design->selected(module, it.second)) + it.second->name = derive_name_from_src(it.second->get_src_attribute(), counter++); + new_wires[it.second->name] = it.second; + } + module->wires_.swap(new_wires); + module->fixup_ports(); + + dict<RTLIL::IdString, RTLIL::Cell*> new_cells; + for (auto &it : module->cells_) { + if (it.first[0] == '$' && design->selected(module, it.second)) + it.second->name = derive_name_from_src(it.second->get_src_attribute(), counter++); + new_cells[it.second->name] = it.second; + } + module->cells_.swap(new_cells); + } + } + else if (flag_enumerate) { extra_args(args, argidx, design); diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index d97aa2b37..ba407ea8c 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -896,6 +896,29 @@ static void select_stmt(RTLIL::Design *design, std::string arg) select_filter_active_mod(design, work_stack.back()); } +static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::Selection *sel) +{ + std::string desc = "Selection contains:\n"; + for (auto mod_it : design->modules_) + { + if (sel->selected_module(mod_it.first)) { + for (auto &it : mod_it.second->wires_) + if (sel->selected_member(mod_it.first, it.first)) + desc += stringf("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); + for (auto &it : mod_it.second->memories) + if (sel->selected_member(mod_it.first, it.first)) + desc += stringf("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); + for (auto &it : mod_it.second->cells_) + if (sel->selected_member(mod_it.first, it.first)) + desc += stringf("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); + for (auto &it : mod_it.second->processes) + if (sel->selected_member(mod_it.first, it.first)) + desc += stringf("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); + } + } + return desc; +} + PRIVATE_NAMESPACE_END YOSYS_NAMESPACE_BEGIN @@ -1394,7 +1417,12 @@ struct SelectPass : public Pass { log_cmd_error("No selection to check.\n"); work_stack.back().optimize(design); if (!work_stack.back().empty()) - log_error("Assertion failed: selection is not empty:%s\n", sel_str.c_str()); + { + RTLIL::Selection *sel = &work_stack.back(); + sel->optimize(design); + std::string desc = describe_selection_for_assert(design, sel); + log_error("Assertion failed: selection is not empty:%s\n%s", sel_str.c_str(), desc.c_str()); + } return; } @@ -1404,7 +1432,12 @@ struct SelectPass : public Pass { log_cmd_error("No selection to check.\n"); work_stack.back().optimize(design); if (work_stack.back().empty()) - log_error("Assertion failed: selection is empty:%s\n", sel_str.c_str()); + { + RTLIL::Selection *sel = &work_stack.back(); + sel->optimize(design); + std::string desc = describe_selection_for_assert(design, sel); + log_error("Assertion failed: selection is empty:%s\n%s", sel_str.c_str(), desc.c_str()); + } return; } @@ -1431,14 +1464,23 @@ struct SelectPass : public Pass { total_count++; } if (assert_count >= 0 && assert_count != total_count) - log_error("Assertion failed: selection contains %d elements instead of the asserted %d:%s\n", - total_count, assert_count, sel_str.c_str()); + { + std::string desc = describe_selection_for_assert(design, sel); + log_error("Assertion failed: selection contains %d elements instead of the asserted %d:%s\n%s", + total_count, assert_count, sel_str.c_str(), desc.c_str()); + } if (assert_max >= 0 && assert_max < total_count) - log_error("Assertion failed: selection contains %d elements, more than the maximum number %d:%s\n", - total_count, assert_max, sel_str.c_str()); + { + std::string desc = describe_selection_for_assert(design, sel); + log_error("Assertion failed: selection contains %d elements, more than the maximum number %d:%s\n%s", + total_count, assert_max, sel_str.c_str(), desc.c_str()); + } if (assert_min >= 0 && assert_min > total_count) - log_error("Assertion failed: selection contains %d elements, less than the minimum number %d:%s\n", - total_count, assert_min, sel_str.c_str()); + { + std::string desc = describe_selection_for_assert(design, sel); + log_error("Assertion failed: selection contains %d elements, less than the minimum number %d:%s\n%s", + total_count, assert_min, sel_str.c_str(), desc.c_str()); + } return; } diff --git a/passes/equiv/Makefile.inc b/passes/equiv/Makefile.inc index dd7b3be02..27ea54b22 100644 --- a/passes/equiv/Makefile.inc +++ b/passes/equiv/Makefile.inc @@ -9,4 +9,4 @@ OBJS += passes/equiv/equiv_induct.o OBJS += passes/equiv/equiv_struct.o OBJS += passes/equiv/equiv_purge.o OBJS += passes/equiv/equiv_mark.o - +OBJS += passes/equiv/equiv_opt.o diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index b1f88d55e..dbd8682e6 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -40,6 +40,16 @@ struct EquivMakeWorker pool<SigBit> undriven_bits; SigMap assign_map; + dict<SigBit, pool<Cell*>> bit2driven; // map: bit <--> and its driven cells + + CellTypes comb_ct; + + EquivMakeWorker() + { + comb_ct.setup_internals(); + comb_ct.setup_stdcells(); + } + void read_blacklists() { for (auto fn : blacklists) @@ -278,16 +288,31 @@ struct EquivMakeWorker } } + init_bit2driven(); + + pool<Cell*> visited_cells; for (auto c : cells_list) for (auto &conn : c->connections()) if (!ct.cell_output(c->type, conn.first)) { SigSpec old_sig = assign_map(conn.second); SigSpec new_sig = rd_signal_map(old_sig); - if (old_sig != new_sig) { - log("Changing input %s of cell %s (%s): %s -> %s\n", - log_id(conn.first), log_id(c), log_id(c->type), - log_signal(old_sig), log_signal(new_sig)); - c->setPort(conn.first, new_sig); + + if(old_sig != new_sig) { + SigSpec tmp_sig = old_sig; + for (int i = 0; i < GetSize(old_sig); i++) { + SigBit old_bit = old_sig[i], new_bit = new_sig[i]; + + visited_cells.clear(); + if (check_signal_in_fanout(visited_cells, old_bit, new_bit)) + continue; + + log("Changing input %s of cell %s (%s): %s -> %s\n", + log_id(conn.first), log_id(c), log_id(c->type), + log_signal(old_bit), log_signal(new_bit)); + + tmp_sig[i] = new_bit; + } + c->setPort(conn.first, tmp_sig); } } @@ -378,6 +403,57 @@ struct EquivMakeWorker } } + void init_bit2driven() + { + for (auto cell : equiv_mod->cells()) { + if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_")) + continue; + for (auto &conn : cell->connections()) + { + if (yosys_celltypes.cell_input(cell->type, conn.first)) + for (auto bit : assign_map(conn.second)) + { + bit2driven[bit].insert(cell); + } + } + } + } + + bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit) + { + if (source_bit == target_bit) + return true; + + if (bit2driven.count(source_bit) == 0) + return false; + + auto driven_cells = bit2driven.at(source_bit); + for (auto driven_cell: driven_cells) + { + bool is_comb = comb_ct.cell_known(driven_cell->type); + if (!is_comb) + continue; + + if (visited_cells.count(driven_cell) > 0) + continue; + visited_cells.insert(driven_cell); + + for (auto &conn: driven_cell->connections()) + { + if (yosys_celltypes.cell_input(driven_cell->type, conn.first)) + continue; + + for (auto bit: conn.second) { + bool is_in_fanout = check_signal_in_fanout(visited_cells, bit, target_bit); + if (is_in_fanout == true) + return true; + } + } + } + + return false; + } + void run() { copy_to_equiv(); diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc new file mode 100644 index 000000000..86550a69b --- /dev/null +++ b/passes/equiv/equiv_opt.cc @@ -0,0 +1,157 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2018 whitequark <whitequark@whitequark.org> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct EquivOptPass:public ScriptPass +{ + EquivOptPass() : ScriptPass("equiv_opt", "prove equivalence for optimized circuit") { } + + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" equiv_opt [options] [command]\n"); + log("\n"); + log("This command checks circuit equivalence before and after an optimization pass.\n"); + log("\n"); + log(" -run <from_label>:<to_label>\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to the start of the command list, and empty to\n"); + log(" label is synonymous to the end of the command list.\n"); + log("\n"); + log(" -map <filename>\n"); + log(" expand the modules in this file before proving equivalence. this is\n"); + log(" useful for handling architecture-specific primitives.\n"); + log("\n"); + log(" -assert\n"); + log(" produce an error if the circuits are not equivalent\n"); + log("\n"); + log("The following commands are executed by this verification command:\n"); + help_script(); + log("\n"); + } + + std::string command, techmap_opts; + bool assert; + + void clear_flags() YS_OVERRIDE + { + command = ""; + techmap_opts = ""; + assert = false; + } + + void execute(std::vector < std::string > args, RTLIL::Design * design) YS_OVERRIDE + { + string run_from, run_to; + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-run" && argidx + 1 < args.size()) { + size_t pos = args[argidx + 1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos + 1); + continue; + } + if (args[argidx] == "-map" && argidx + 1 < args.size()) { + techmap_opts += " -map " + args[++argidx]; + continue; + } + if (args[argidx] == "-assert") { + assert = true; + continue; + } + break; + } + + for (; argidx < args.size(); argidx++) { + if (command.empty()) { + if (args[argidx].substr(0, 1) == "-") + cmd_error(args, argidx, "Unknown option."); + } else { + command += " "; + } + command += args[argidx]; + } + + if (command.empty()) + log_cmd_error("No optimization pass specified!\n"); + + if (!design->full_selection()) + log_cmd_error("This command only operates on fully selected designs!\n"); + + log_header(design, "Executing EQUIV_OPT pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + + log_pop(); + } + + void script() YS_OVERRIDE + { + if (check_label("run_pass")) { + run("hierarchy -auto-top"); + run("design -save preopt"); + if (help_mode) + run("[command]"); + else + run(command); + run("design -stash postopt"); + } + + if (check_label("prepare")) { + run("design -copy-from preopt -as gold A:top"); + run("design -copy-from postopt -as gate A:top"); + } + + if ((!techmap_opts.empty() || help_mode) && check_label("techmap", "(only with -map)")) { + string opts; + if (help_mode) + opts = " -map <filename> ..."; + else + opts = techmap_opts; + run("techmap -D EQUIV -autoproc" + opts); + } + + if (check_label("prove")) { + run("equiv_make gold gate equiv"); + run("equiv_induct equiv"); + if (help_mode) + run("equiv_status [-assert] equiv"); + else if (assert) + run("equiv_status -assert equiv"); + else + run("equiv_status equiv"); + } + + if (check_label("restore")) { + run("design -load preopt"); + } + } +} EquivOptPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 5df69848e..0c782b8ab 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2018 Ruben Undheim <ruben.undheim@gmail.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -145,9 +146,36 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check std::map<RTLIL::Cell*, std::pair<int, int>> array_cells; std::string filename; + bool has_interface_ports = false; + + // If any of the ports are actually interface ports, we will always need to + // reprocess the module: + if(!module->get_bool_attribute("\\interfaces_replaced_in_module")) { + for (auto &wire : module->wires_) { + if ((wire.second->port_input || wire.second->port_output) && wire.second->get_bool_attribute("\\is_interface")) + has_interface_ports = true; + } + } + + // Always keep track of all derived interfaces available in the current module in 'interfaces_in_module': + dict<RTLIL::IdString, RTLIL::Module*> interfaces_in_module; + for (auto &cell_it : module->cells_) + { + RTLIL::Cell *cell = cell_it.second; + if(cell->get_bool_attribute("\\is_interface")) { + RTLIL::Module *intf_module = design->modules_[cell->type]; + interfaces_in_module[cell->name] = intf_module; + } + } + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; + bool has_interfaces_not_found = false; + + std::vector<RTLIL::IdString> connections_to_remove; + std::vector<RTLIL::IdString> connections_to_add_name; + std::vector<RTLIL::SigSpec> connections_to_add_signal; if (cell->type.substr(0, 7) == "$array:") { int pos_idx = cell->type.str().find_first_of(':'); @@ -158,6 +186,8 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check array_cells[cell] = std::pair<int, int>(idx, num); cell->type = cell->type.str().substr(pos_type + 1); } + dict<RTLIL::IdString, RTLIL::Module*> interfaces_to_add_to_submodule; + dict<RTLIL::IdString, RTLIL::IdString> modports_used_in_submodule; if (design->modules_.count(cell->type) == 0) { @@ -200,11 +230,85 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check if (design->modules_.count(cell->type) == 0) log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str()); did_something = true; - } else + } else { + + RTLIL::Module *mod = design->module(cell->type); + + // Go over all connections and see if any of them are SV interfaces. If they are, then add the replacements to + // some lists, so that the ports for sub-modules can be replaced further down: + for (auto &conn : cell->connections()) { + if(mod->wires_.count(conn.first) != 0 && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list + //const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_type"); + //for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness) + //} + + // Find if the sub-module has set a modport for the current interface connection: + const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_modport"); + std::string interface_modport = ""; + for (auto &d : interface_modport_pool) { + interface_modport = "\\" + d; + } + if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute("\\is_interface")) { // Check if the connected wire is a potential interface in the parent module + std::string interface_name_str = conn.second.bits()[0].wire->name.str(); + interface_name_str.replace(0,23,""); // Strip the prefix '$dummywireforinterface' from the dummy wire to get the name + interface_name_str = "\\" + interface_name_str; + RTLIL::IdString interface_name = interface_name_str; + bool not_found_interface = false; + if(module->get_bool_attribute("\\interfaces_replaced_in_module")) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either + // Check if the interface instance is present in module: + // Interface instances may either have the plain name or the name appended with '_inst_from_top_dummy'. + // Check for both of them here + int nexactmatch = interfaces_in_module.count(interface_name) > 0; + std::string interface_name_str2 = interface_name_str + "_inst_from_top_dummy"; + RTLIL::IdString interface_name2 = interface_name_str2; + int nmatch2 = interfaces_in_module.count(interface_name2) > 0; + if (nexactmatch > 0 || nmatch2 > 0) { + if (nexactmatch != 0) // Choose the one with the plain name if it exists + interface_name2 = interface_name; + RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name2); + for (auto &mod_wire : mod_replace_ports->wires_) { // Go over all wires in interface, and add replacements to lists. + std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire.first); + std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire.first); + connections_to_add_name.push_back(RTLIL::IdString(signal_name1)); + if(module->wires_.count(signal_name2) == 0) { + log_error("Could not find signal '%s' in '%s'\n", signal_name2.c_str(), log_id(module->name)); + } + else { + RTLIL::Wire *wire_in_parent = module->wire(signal_name2); + connections_to_add_signal.push_back(wire_in_parent); + } + } + connections_to_remove.push_back(conn.first); + interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name2); + + // Add modports to a dict which will be passed to AstModule::derive + if (interface_modport != "") { + modports_used_in_submodule[conn.first] = interface_modport; + } + } + else not_found_interface = true; + } + else not_found_interface = true; + // If the interface instance has not already been derived in the module, we cannot complete at this stage. Set "has_interfaces_not_found" + // which will delay the expansion of this cell: + if (not_found_interface) { + // If we have already gone over all cells in this module, and the interface has still not been found - flag it as an error: + if(!(module->get_bool_attribute("\\cells_not_processed"))) { + log_warning("Could not find interface instance for `%s' in `%s'\n", log_id(interface_name), log_id(module)); + } + else { + // Only set has_interfaces_not_found if it would be possible to find them, since otherwiser we will end up in an infinite loop: + has_interfaces_not_found = true; + } + } + } + } + } + // + if (flag_check || flag_simcheck) { - RTLIL::Module *mod = design->module(cell->type); - for (auto &conn : cell->connections()) + for (auto &conn : cell->connections()) { if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { int id = atoi(conn.first.c_str()+1); if (id <= 0 || id > GetSize(mod->ports)) @@ -213,11 +317,15 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check } else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0) log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first)); + } for (auto ¶m : cell->parameters) if (mod->avail_parameters.count(param.first) == 0 && param.first[0] != '$' && strchr(param.first.c_str(), '.') == NULL) log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a parameter named '%s'.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(param.first)); + } + } + RTLIL::Module *mod = design->modules_[cell->type]; if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) { if (flag_simcheck) @@ -226,14 +334,61 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check continue; } - if (cell->parameters.size() == 0) + // If interface instances not yet found, skip cell for now, and say we did something, so that we will return back here: + if(has_interfaces_not_found) { + did_something = true; // waiting for interfaces to be handled continue; + } - RTLIL::Module *mod = design->modules_[cell->type]; - cell->type = mod->derive(design, cell->parameters); + // Do the actual replacements of the SV interface port connection with the individual signal connections: + for(unsigned int i=0;i<connections_to_add_name.size();i++) { + cell->connections_[connections_to_add_name[i]] = connections_to_add_signal[i]; + } + // Remove the connection for the interface itself: + for(unsigned int i=0;i<connections_to_remove.size();i++) { + cell->connections_.erase(connections_to_remove[i]); + } + + // If there are no overridden parameters AND not interfaces, then we can use the existing module instance as the type + // for the cell: + if (cell->parameters.size() == 0 && (interfaces_to_add_to_submodule.size() == 0 || !(cell->get_bool_attribute("\\module_not_derived")))) { + // If the cell being processed is an the interface instance itself, go down to "handle_interface_instance:", + // so that the signals of the interface are added to the parent module. + if (mod->get_bool_attribute("\\is_interface")) { + goto handle_interface_instance; + } + continue; + } + + cell->type = mod->derive(design, cell->parameters, interfaces_to_add_to_submodule, modports_used_in_submodule); cell->parameters.clear(); did_something = true; + + handle_interface_instance: + + // We add all the signals of the interface explicitly to the parent module. This is always needed when we encounter + // an interface instance: + if (mod->get_bool_attribute("\\is_interface") && cell->get_bool_attribute("\\module_not_derived")) { + cell->set_bool_attribute("\\is_interface"); + RTLIL::Module *derived_module = design->modules_[cell->type]; + interfaces_in_module[cell->name] = derived_module; + did_something = true; + } + // We clear 'module_not_derived' such that we will not rederive the cell again (needed when there are interfaces connected to the cell) + cell->attributes.erase("\\module_not_derived"); } + // Clear the attribute 'cells_not_processed' such that it can be known that we + // have been through all cells at least once, and that we can know whether + // to flag an error because of interface instances not found: + module->attributes.erase("\\cells_not_processed"); + + + // If any interface instances or interface ports were found in the module, we need to rederive it completely: + if ((interfaces_in_module.size() > 0 || has_interface_ports) && !module->get_bool_attribute("\\interfaces_replaced_in_module")) { + module->reprocess_module(design, interfaces_in_module); + return did_something; + } + for (auto &it : array_cells) { @@ -303,6 +458,20 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) for (auto &it : design->modules_) if (used.count(it.second) == 0) del_modules.push_back(it.second); + else { + // Now all interface ports must have been exploded, and it is hence + // safe to delete all of the remaining dummy interface ports: + pool<RTLIL::Wire*> del_wires; + for(auto &wire : it.second->wires_) { + if ((wire.second->port_input || wire.second->port_output) && wire.second->get_bool_attribute("\\is_interface")) { + del_wires.insert(wire.second); + } + } + if (del_wires.size() > 0) { + it.second->remove(del_wires); + it.second->fixup_ports(); + } + } int del_counter = 0; for (auto mod : del_modules) { @@ -341,6 +510,20 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db) return db.at(module); } +RTLIL::Module *check_if_top_has_changed(Design *design, Module *top_mod) +{ + if(top_mod != NULL && top_mod->get_bool_attribute("\\initial_top")) + return top_mod; + else { + for (auto mod : design->modules()) { + if (mod->get_bool_attribute("\\top")) { + return mod; + } + } + } + return NULL; +} + struct HierarchyPass : public Pass { HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { } void help() YS_OVERRIDE @@ -568,6 +751,14 @@ struct HierarchyPass : public Pass { if (flag_simcheck && top_mod == nullptr) log_error("Design has no top module.\n"); + if (top_mod != NULL) { + for (auto &mod_it : design->modules_) + if (mod_it.second == top_mod) + mod_it.second->attributes["\\initial_top"] = RTLIL::Const(1); + else + mod_it.second->attributes.erase("\\initial_top"); + } + bool did_something = true; while (did_something) { @@ -586,19 +777,43 @@ struct HierarchyPass : public Pass { if (expand_module(design, module, flag_check, flag_simcheck, libdirs)) did_something = true; } + + + // The top module might have changed if interface instances have been detected in it: + RTLIL::Module *tmp_top_mod = check_if_top_has_changed(design, top_mod); + if (tmp_top_mod != NULL) { + if (tmp_top_mod != top_mod){ + top_mod = tmp_top_mod; + did_something = true; + } + } + + // Delete modules marked as 'to_delete': + std::vector<RTLIL::Module *> modules_to_delete; + for(auto &mod_it : design->modules_) { + if (mod_it.second->get_bool_attribute("\\to_delete")) { + modules_to_delete.push_back(mod_it.second); + } + } + for(size_t i=0; i<modules_to_delete.size(); i++) { + design->remove(modules_to_delete[i]); + } } + if (top_mod != NULL) { log_header(design, "Analyzing design hierarchy..\n"); hierarchy_clean(design, top_mod, purge_lib); } if (top_mod != NULL) { - for (auto &mod_it : design->modules_) + for (auto &mod_it : design->modules_) { if (mod_it.second == top_mod) mod_it.second->attributes["\\top"] = RTLIL::Const(1); else mod_it.second->attributes.erase("\\top"); + mod_it.second->attributes.erase("\\initial_top"); + } } if (!nokeep_asserts) { diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index e8552bbcf..cf4095d06 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -472,8 +472,12 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, std::vector<SigSpec> new_wr_en(GetSize(old_wr_en)); std::vector<SigSpec> new_wr_data(GetSize(old_wr_data)); std::vector<SigSpec> new_rd_data(GetSize(old_rd_data)); + std::vector<std::vector<State>> new_initdata; std::vector<int> shuffle_map; + if (cell_init) + new_initdata.resize(mem_size); + for (auto &it : en_order) { auto &bits = bits_wr_en.at(it); @@ -489,6 +493,10 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, } for (int j = 0; j < rd_ports; j++) new_rd_data[j].append(old_rd_data[j][bits[i]]); + if (cell_init) { + for (int j = 0; j < mem_size; j++) + new_initdata[j].push_back(initdata[j][bits[i]]); + } shuffle_map.push_back(bits[i]); } @@ -499,6 +507,10 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, } for (int j = 0; j < rd_ports; j++) new_rd_data[j].append(State::Sx); + if (cell_init) { + for (int j = 0; j < mem_size; j++) + new_initdata[j].push_back(State::Sx); + } shuffle_map.push_back(-1); } } @@ -522,6 +534,11 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, for (int i = 0; i < rd_ports; i++) rd_data.replace(i*mem_width, new_rd_data[i]); + + if (cell_init) { + for (int i = 0; i < mem_size; i++) + initdata[i] = Const(new_initdata[i]); + } } // assign write ports @@ -623,6 +640,7 @@ grow_read_ports:; pi.sig_addr = SigSpec(); pi.sig_data = SigSpec(); pi.sig_en = SigSpec(); + pi.make_outreg = false; } new_portinfos.push_back(pi); if (pi.dupidx == dup_count-1) { diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 32df19174..220d29295 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -41,7 +41,7 @@ struct MemoryDffWorker if (wire->attributes.count("\\init") == 0) continue; SigSpec sig = sigmap(wire); - Const initval = wire->attributes.count("\\init"); + Const initval = wire->attributes.at("\\init"); for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++) if (initval[i] == State::S0 || initval[i] == State::S1) init_bits.insert(sig[i]); diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index 0d01e9d35..0f596b1f4 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -6,6 +6,7 @@ OBJS += passes/opt/opt_reduce.o OBJS += passes/opt/opt_rmdff.o OBJS += passes/opt/opt_clean.o OBJS += passes/opt/opt_expr.o +OBJS += passes/opt/opt_lut.o ifneq ($(SMALL),1) OBJS += passes/opt/share.o diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 0ba233c62..610edc5e9 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1406,7 +1406,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false) { if (sigConst.is_fully_zero()) { - RTLIL::SigSpec a_prime(RTLIL::State::S0, 1); + RTLIL::SigSpec a_prime(RTLIL::State::S0, GetSize(cell->getPort("\\Y"))); if (is_lt) { log("Replacing %s cell `%s' (implementing unsigned X<0) with constant false.\n", log_id(cell->type), log_id(cell)); diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc new file mode 100644 index 000000000..be050c713 --- /dev/null +++ b/passes/opt/opt_lut.cc @@ -0,0 +1,503 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2018 whitequark <whitequark@whitequark.org> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include "kernel/modtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct OptLutWorker +{ + dict<IdString, dict<int, IdString>> &dlogic; + RTLIL::Module *module; + ModIndex index; + SigMap sigmap; + + pool<RTLIL::Cell*> luts; + dict<RTLIL::Cell*, int> luts_arity; + dict<RTLIL::Cell*, pool<RTLIL::Cell*>> luts_dlogics; + dict<RTLIL::Cell*, pool<int>> luts_dlogic_inputs; + + int combined_count = 0; + + bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs) + { + SigSpec lut_input = sigmap(lut->getPort("\\A")); + int lut_width = lut->getParam("\\WIDTH").as_int(); + Const lut_table = lut->getParam("\\LUT"); + int lut_index = 0; + + for (int i = 0; i < lut_width; i++) + { + SigBit input = sigmap(lut_input[i]); + if (inputs.count(input)) + { + lut_index |= inputs[input] << i; + } + else + { + lut_index |= SigSpec(lut_input[i]).as_bool() << i; + } + } + + return lut_table.extract(lut_index).as_bool(); + } + + void show_stats_by_arity() + { + dict<int, int> arity_counts; + dict<IdString, int> dlogic_counts; + int max_arity = 0; + + for (auto lut_arity : luts_arity) + { + max_arity = max(max_arity, lut_arity.second); + arity_counts[lut_arity.second]++; + } + + for (auto &lut_dlogics : luts_dlogics) + { + for (auto &lut_dlogic : lut_dlogics.second) + { + dlogic_counts[lut_dlogic->type]++; + } + } + + log("Number of LUTs: %8zu\n", luts.size()); + for (int arity = 1; arity <= max_arity; arity++) + { + if (arity_counts[arity]) + log(" %d-LUT %16d\n", arity, arity_counts[arity]); + } + for (auto &dlogic_count : dlogic_counts) + { + log(" with %-12s %4d\n", dlogic_count.first.c_str(), dlogic_count.second); + } + } + + OptLutWorker(dict<IdString, dict<int, IdString>> &dlogic, RTLIL::Module *module, int limit) : + dlogic(dlogic), module(module), index(module), sigmap(module) + { + log("Discovering LUTs.\n"); + for (auto cell : module->selected_cells()) + { + if (cell->type == "$lut") + { + int lut_width = cell->getParam("\\WIDTH").as_int(); + SigSpec lut_input = cell->getPort("\\A"); + int lut_arity = 0; + + log("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, log_id(module), log_id(cell)); + luts.insert(cell); + + // First, find all dedicated logic we're connected to. This results in an overapproximation + // of such connections. + pool<RTLIL::Cell*> lut_all_dlogics; + for (int i = 0; i < lut_width; i++) + { + SigBit bit = lut_input[i]; + for (auto &port : index.query_ports(bit)) + { + if (dlogic.count(port.cell->type)) + { + auto &dlogic_map = dlogic[port.cell->type]; + if (dlogic_map.count(i)) + { + if (port.port == dlogic_map[i]) + { + lut_all_dlogics.insert(port.cell); + } + } + } + } + } + + // Second, make sure that the connection to dedicated logic is legal. If it is not legal, + // it means one of the two things: + // * The connection is spurious. I.e. this is dedicated logic that will be packed + // with some other LUT, and it just happens to be conected to this LUT as well. + // * The connection is illegal. + // In either of these cases, we don't need to concern ourselves with preserving the connection + // between this LUT and this dedicated logic cell. + pool<RTLIL::Cell*> lut_legal_dlogics; + pool<int> lut_dlogic_inputs; + for (auto lut_dlogic : lut_all_dlogics) + { + auto &dlogic_map = dlogic[lut_dlogic->type]; + bool legal = true; + for (auto &dlogic_conn : dlogic_map) + { + if (lut_width <= dlogic_conn.first) + { + log(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic->type.c_str(), log_id(module), log_id(lut_dlogic)); + log(" LUT input A[%d] not present.\n", dlogic_conn.first); + legal = false; + break; + } + if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic->getPort(dlogic_conn.second))) + { + log(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic->type.c_str(), log_id(module), log_id(lut_dlogic)); + log(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic->getPort(dlogic_conn.second))); + legal = false; + break; + } + } + + if (legal) + { + log(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic->type.c_str(), log_id(module), log_id(lut_dlogic)); + lut_legal_dlogics.insert(lut_dlogic); + for (auto &dlogic_conn : dlogic_map) + lut_dlogic_inputs.insert(dlogic_conn.first); + } + } + + // Third, determine LUT arity. An n-wide LUT that has k constant inputs and m inputs shared with dedicated + // logic implements an (n-k-m)-ary function. + for (int i = 0; i < lut_width; i++) + { + SigBit bit = lut_input[i]; + if (bit.wire || lut_dlogic_inputs.count(i)) + lut_arity++; + } + + log(" Cell implements a %d-LUT.\n", lut_arity); + luts_arity[cell] = lut_arity; + luts_dlogics[cell] = lut_legal_dlogics; + luts_dlogic_inputs[cell] = lut_dlogic_inputs; + } + } + show_stats_by_arity(); + + log("\n"); + log("Combining LUTs.\n"); + pool<RTLIL::Cell*> worklist = luts; + while (worklist.size()) + { + if (limit == 0) + { + log("Limit reached.\n"); + break; + } + + auto lutA = worklist.pop(); + SigSpec lutA_input = sigmap(lutA->getPort("\\A")); + SigSpec lutA_output = sigmap(lutA->getPort("\\Y")[0]); + int lutA_width = lutA->getParam("\\WIDTH").as_int(); + int lutA_arity = luts_arity[lutA]; + pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA]; + + auto lutA_output_ports = index.query_ports(lutA->getPort("\\Y")); + if (lutA_output_ports.size() != 2) + continue; + + for (auto &port : lutA_output_ports) + { + if (port.cell == lutA) + continue; + + if (luts.count(port.cell)) + { + auto lutB = port.cell; + SigSpec lutB_input = sigmap(lutB->getPort("\\A")); + SigSpec lutB_output = sigmap(lutB->getPort("\\Y")[0]); + int lutB_width = lutB->getParam("\\WIDTH").as_int(); + int lutB_arity = luts_arity[lutB]; + pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB]; + + log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB)); + + if (index.query_is_output(lutA->getPort("\\Y"))) + { + log(" Not combining LUTs (cascade connection feeds module output).\n"); + continue; + } + + pool<SigBit> lutA_inputs; + pool<SigBit> lutB_inputs; + for (auto &bit : lutA_input) + { + if (bit.wire) + lutA_inputs.insert(sigmap(bit)); + } + for (auto &bit : lutB_input) + { + if (bit.wire) + lutB_inputs.insert(sigmap(bit)); + } + + pool<SigBit> common_inputs; + for (auto &bit : lutA_inputs) + { + if (lutB_inputs.count(bit)) + common_inputs.insert(bit); + } + + int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size(); + if (lutA_dlogic_inputs.size()) + log(" Cell A is a %d-LUT with %zu dedicated connections. ", lutA_arity, lutA_dlogic_inputs.size()); + else + log(" Cell A is a %d-LUT. ", lutA_arity); + if (lutB_dlogic_inputs.size()) + log("Cell B is a %d-LUT with %zu dedicated connections.\n", lutB_arity, lutB_dlogic_inputs.size()); + else + log("Cell B is a %d-LUT.\n", lutB_arity); + log(" Cells share %zu input(s) and can be merged into one %d-LUT.\n", common_inputs.size(), lutM_arity); + + const int COMBINE_A = 1, COMBINE_B = 2, COMBINE_EITHER = COMBINE_A | COMBINE_B; + int combine_mask = 0; + if (lutM_arity > lutA_width) + { + log(" Not combining LUTs into cell A (combined LUT wider than cell A).\n"); + } + else if (lutB_dlogic_inputs.size() > 0) + { + log(" Not combining LUTs into cell A (cell B is connected to dedicated logic).\n"); + } + else if (lutB->get_bool_attribute("\\lut_keep")) + { + log(" Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n"); + } + else + { + combine_mask |= COMBINE_A; + } + if (lutM_arity > lutB_width) + { + log(" Not combining LUTs into cell B (combined LUT wider than cell B).\n"); + } + else if (lutA_dlogic_inputs.size() > 0) + { + log(" Not combining LUTs into cell B (cell A is connected to dedicated logic).\n"); + } + else if (lutA->get_bool_attribute("\\lut_keep")) + { + log(" Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n"); + } + else + { + combine_mask |= COMBINE_B; + } + + int combine = combine_mask; + if (combine == COMBINE_EITHER) + { + log(" Can combine into either cell.\n"); + if (lutA_arity == 1) + { + log(" Cell A is a buffer or inverter, combining into cell B.\n"); + combine = COMBINE_B; + } + else if (lutB_arity == 1) + { + log(" Cell B is a buffer or inverter, combining into cell A.\n"); + combine = COMBINE_A; + } + else + { + log(" Arbitrarily combining into cell A.\n"); + combine = COMBINE_A; + } + } + + RTLIL::Cell *lutM, *lutR; + pool<SigBit> lutM_inputs, lutR_inputs; + pool<int> lutM_dlogic_inputs; + if (combine == COMBINE_A) + { + log(" Combining LUTs into cell A.\n"); + lutM = lutA; + lutM_inputs = lutA_inputs; + lutM_dlogic_inputs = lutA_dlogic_inputs; + lutR = lutB; + lutR_inputs = lutB_inputs; + } + else if (combine == COMBINE_B) + { + log(" Combining LUTs into cell B.\n"); + lutM = lutB; + lutM_inputs = lutB_inputs; + lutM_dlogic_inputs = lutB_dlogic_inputs; + lutR = lutA; + lutR_inputs = lutA_inputs; + } + else + { + log(" Cannot combine LUTs.\n"); + continue; + } + + pool<SigBit> lutR_unique; + for (auto &bit : lutR_inputs) + { + if (!common_inputs.count(bit) && bit != lutA_output) + lutR_unique.insert(bit); + } + + int lutM_width = lutM->getParam("\\WIDTH").as_int(); + SigSpec lutM_input = sigmap(lutM->getPort("\\A")); + std::vector<SigBit> lutM_new_inputs; + for (int i = 0; i < lutM_width; i++) + { + bool input_unused = false; + if (sigmap(lutM_input[i]) == lutA_output) + input_unused = true; + if (!lutM_input[i].wire && !lutM_dlogic_inputs.count(i)) + input_unused = true; + + if (input_unused && lutR_unique.size()) + { + SigBit new_input = lutR_unique.pop(); + log(" Connecting input %d as %s.\n", i, log_signal(new_input)); + lutM_new_inputs.push_back(new_input); + } + else if (sigmap(lutM_input[i]) == lutA_output) + { + log(" Disconnecting cascade input %d.\n", i); + lutM_new_inputs.push_back(SigBit()); + } + else + { + log(" Leaving input %d as %s.\n", i, log_signal(lutM_input[i])); + lutM_new_inputs.push_back(lutM_input[i]); + } + } + log_assert(lutR_unique.size() == 0); + + RTLIL::Const lutM_new_table(State::Sx, 1 << lutM_width); + for (int eval = 0; eval < 1 << lutM_width; eval++) + { + dict<SigBit, bool> eval_inputs; + for (size_t i = 0; i < lutM_new_inputs.size(); i++) + { + eval_inputs[lutM_new_inputs[i]] = (eval >> i) & 1; + } + eval_inputs[lutA_output] = evaluate_lut(lutA, eval_inputs); + lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs); + } + + log(" Cell A truth table: %s.\n", lutA->getParam("\\LUT").as_string().c_str()); + log(" Cell B truth table: %s.\n", lutB->getParam("\\LUT").as_string().c_str()); + log(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str()); + + lutM->setParam("\\LUT", lutM_new_table); + lutM->setPort("\\A", lutM_new_inputs); + lutM->setPort("\\Y", lutB_output); + + luts_arity[lutM] = lutM_arity; + luts.erase(lutR); + luts_arity.erase(lutR); + lutR->module->remove(lutR); + + worklist.insert(lutM); + worklist.erase(lutR); + + combined_count++; + if (limit > 0) + limit--; + } + } + } + show_stats_by_arity(); + } +}; + +static void split(std::vector<std::string> &tokens, const std::string &text, char sep) +{ + size_t start = 0, end = 0; + while ((end = text.find(sep, start)) != std::string::npos) { + tokens.push_back(text.substr(start, end - start)); + start = end + 1; + } + tokens.push_back(text.substr(start)); +} + +struct OptLutPass : public Pass { + OptLutPass() : Pass("opt_lut", "optimize LUT cells") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" opt_lut [options] [selection]\n"); + log("\n"); + log("This pass combines cascaded $lut cells with unused inputs.\n"); + log("\n"); + log(" -dlogic <type>:<cell-port>=<LUT-input>[:<cell-port>=<LUT-input>...]\n"); + log(" preserve connections to dedicated logic cell <type> that has ports\n"); + log(" <cell-port> connected to LUT inputs <LUT-input>. this includes\n"); + log(" the case where both LUT and dedicated logic input are connected to\n"); + log(" the same constant.\n"); + log("\n"); + log(" -limit N\n"); + log(" only perform the first N combines, then stop. useful for debugging.\n"); + log("\n"); + } + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n"); + + dict<IdString, dict<int, IdString>> dlogic; + int limit = -1; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-dlogic" && argidx+1 < args.size()) + { + std::vector<std::string> tokens; + split(tokens, args[++argidx], ':'); + if (tokens.size() < 2) + log_cmd_error("The -dlogic option requires at least one connection.\n"); + IdString type = "\\" + tokens[0]; + for (auto it = tokens.begin() + 1; it != tokens.end(); ++it) { + std::vector<std::string> conn_tokens; + split(conn_tokens, *it, '='); + if (conn_tokens.size() != 2) + log_cmd_error("Invalid format of -dlogic signal mapping.\n"); + IdString logic_port = "\\" + conn_tokens[0]; + int lut_input = atoi(conn_tokens[1].c_str()); + dlogic[type][lut_input] = logic_port; + } + continue; + } + if (args[argidx] == "-limit" && argidx + 1 < args.size()) + { + limit = atoi(args[++argidx].c_str()); + continue; + } + break; + } + extra_args(args, argidx, design); + + int total_count = 0; + for (auto module : design->selected_modules()) + { + OptLutWorker worker(dlogic, module, limit - total_count); + total_count += worker.combined_count; + } + if (total_count) + design->scratchpad_set_bool("opt.did_something", true); + log("\n"); + log("Combined %d LUTs.\n", total_count); + } +} OptLutPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 87c7ce9b2..375697dc8 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -36,6 +36,7 @@ struct OptMuxtreeWorker RTLIL::Module *module; SigMap assign_map; int removed_count; + int glob_abort_cnt = 100000; struct bitinfo_t { bool seen_non_mux; @@ -293,6 +294,9 @@ struct OptMuxtreeWorker void eval_mux_port(knowledge_t &knowledge, int mux_idx, int port_idx, bool do_replace_known, bool do_enable_ports, int abort_count) { + if (glob_abort_cnt == 0) + return; + muxinfo_t &muxinfo = mux2info[mux_idx]; if (do_enable_ports) @@ -315,7 +319,7 @@ struct OptMuxtreeWorker knowledge.visited_muxes[m] = true; parent_muxes.push_back(m); } - for (int m : parent_muxes) + for (int m : parent_muxes) { if (root_enable_muxes.at(m)) continue; else if (root_muxes.at(m)) { @@ -327,6 +331,9 @@ struct OptMuxtreeWorker eval_mux(knowledge, m, false, do_enable_ports, abort_count - 1); } else eval_mux(knowledge, m, do_replace_known, do_enable_ports, abort_count); + if (glob_abort_cnt == 0) + return; + } for (int m : parent_muxes) knowledge.visited_muxes[m] = false; @@ -390,6 +397,12 @@ struct OptMuxtreeWorker void eval_mux(knowledge_t &knowledge, int mux_idx, bool do_replace_known, bool do_enable_ports, int abort_count) { + if (glob_abort_cnt == 0) { + log(" Giving up (too many iterations)\n"); + return; + } + glob_abort_cnt--; + muxinfo_t &muxinfo = mux2info[mux_idx]; // set input ports to constants if we find known active or inactive signals @@ -433,6 +446,9 @@ struct OptMuxtreeWorker if (knowledge.known_inactive.at(portinfo.ctrl_sig)) continue; eval_mux_port(knowledge, mux_idx, port_idx, do_replace_known, do_enable_ports, abort_count); + + if (glob_abort_cnt == 0) + return; } } diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index 9f0c7bf67..47d0ff416 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -83,9 +83,9 @@ struct DeminoutPass : public Pass { for (auto bit : sigmap(conn.second)) bits_used.insert(bit); - if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_")) + if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_", "$tribuf")) { - bool tribuf = (cell->type == "$_TBUF_"); + bool tribuf = (cell->type == "$_TBUF_" || cell->type == "$tribuf"); if (!tribuf) { for (auto &c : cell->connections()) { @@ -113,7 +113,8 @@ struct DeminoutPass : public Pass { { if (bits_numports[bit] > 1 || bits_inout.count(bit)) new_input = true, new_output = true; - + if (bit == State::S0 || bit == State::S1) + new_output = true; if (bits_written.count(bit)) { new_output = true; if (bits_tribuf.count(bit)) diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 3291f5a4a..7e1040963 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -267,6 +267,10 @@ struct Dff2dffePass : public Pass { log(" operate in the opposite direction: replace $dffe cells with combinations\n"); log(" of $dff and $mux cells. the options below are ignore in unmap mode.\n"); log("\n"); + log(" -unmap-mince N\n"); + log(" Same as -unmap but only unmap $dffe where the clock enable port\n"); + log(" signal is used by less $dffe than the specified number\n"); + log("\n"); log(" -direct <internal_gate_type> <external_gate_type>\n"); log(" map directly to external gate type. <internal_gate_type> can\n"); log(" be any internal gate-level FF cell (except $_DFFE_??_). the\n"); @@ -289,6 +293,7 @@ struct Dff2dffePass : public Pass { log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n"); bool unmap_mode = false; + int min_ce_use = -1; dict<IdString, IdString> direct_dict; size_t argidx; @@ -297,6 +302,11 @@ struct Dff2dffePass : public Pass { unmap_mode = true; continue; } + if (args[argidx] == "-unmap-mince" && argidx + 1 < args.size()) { + unmap_mode = true; + min_ce_use = std::stoi(args[++argidx]); + continue; + } if (args[argidx] == "-direct" && argidx + 2 < args.size()) { string direct_from = RTLIL::escape_id(args[++argidx]); string direct_to = RTLIL::escape_id(args[++argidx]); @@ -343,8 +353,21 @@ struct Dff2dffePass : public Pass { if (!mod->has_processes_warn()) { if (unmap_mode) { + SigMap sigmap(mod); for (auto cell : mod->selected_cells()) { if (cell->type == "$dffe") { + if (min_ce_use >= 0) { + int ce_use = 0; + for (auto cell_other : mod->selected_cells()) { + if (cell_other->type != cell->type) + continue; + if (sigmap(cell->getPort("\\EN")) == sigmap(cell_other->getPort("\\EN"))) + ce_use++; + } + if (ce_use >= min_ce_use) + continue; + } + RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort("\\D"))); mod->addDff(NEW_ID, cell->getPort("\\CLK"), tmp, cell->getPort("\\Q"), cell->getParam("\\CLK_POLARITY").as_bool()); if (cell->getParam("\\EN_POLARITY").as_bool()) @@ -355,6 +378,18 @@ struct Dff2dffePass : public Pass { continue; } if (cell->type.substr(0, 7) == "$_DFFE_") { + if (min_ce_use >= 0) { + int ce_use = 0; + for (auto cell_other : mod->selected_cells()) { + if (cell_other->type != cell->type) + continue; + if (sigmap(cell->getPort("\\E")) == sigmap(cell_other->getPort("\\E"))) + ce_use++; + } + if (ce_use >= min_ce_use) + continue; + } + bool clk_pol = cell->type.substr(7, 1) == "P"; bool en_pol = cell->type.substr(8, 1) == "P"; RTLIL::SigSpec tmp = mod->addWire(NEW_ID); diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 416ed2bd5..b0528d473 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -100,6 +100,18 @@ static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, for (auto child : cell->children) if (child->id == "pin" && child->args.size() == 1 && child->args[0] == pin_name) return true; + + /* If we end up here, the pin specified in the attribute does not exist, which is an error, + or, the attribute contains an expression which we do not yet support. + For now, we'll simply produce a warning to let the user know something is up. + */ + if (pin_name.find_first_of("^*|&") == std::string::npos) { + log_warning("Malformed liberty file - cannot find pin '%s' in cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str()); + } + else { + log_warning("Found unsupported expression '%s' in pin attribute of cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str()); + } + return false; } diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index d3b1ff02f..3927a657b 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -90,11 +90,11 @@ int LibertyParser::lexer(std::string &str) c = f.get(); } while (c == ' ' || c == '\t' || c == '\r'); - if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') { + if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.' || c == '[' || c == ']') { str = c; while (1) { c = f.get(); - if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') + if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.' || c == '[' || c == ']') str += c; else break; @@ -159,7 +159,7 @@ int LibertyParser::lexer(std::string &str) if (c == '\n') { line++; - return ';'; + return 'n'; } // if (c >= 32 && c < 255) @@ -175,7 +175,7 @@ LibertyAst *LibertyParser::parse() int tok = lexer(str); - while (tok == ';') + while (tok == 'n') tok = lexer(str); if (tok == '}' || tok < 0) @@ -194,6 +194,9 @@ LibertyAst *LibertyParser::parse() if (tok == ';') break; + if (tok == 'n') + continue; + if (tok == ':' && ast->value.empty()) { tok = lexer(ast->value); if (tok != 'v') @@ -249,14 +252,14 @@ LibertyAst *LibertyParser::parse() void LibertyParser::error() { - log_error("Syntax error in line %d.\n", line); + log_error("Syntax error in liberty file on line %d.\n", line); } #else void LibertyParser::error() { - fprintf(stderr, "Syntax error in line %d.\n", line); + fprintf(stderr, "Syntax error in liberty file on line %d.\n", line); exit(1); } diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index d32bbff14..a4ed79550 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -32,7 +32,7 @@ int lut2mux(Cell *cell) if (GetSize(sig_a) == 1) { - cell->module->addMuxGate(NEW_ID, lut[0], lut[1], sig_a, sig_y); + cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); } else { |