diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/select.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm.cc | 9 | ||||
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 9 | ||||
| -rw-r--r-- | passes/sat/sim.cc | 2 |
4 files changed, 21 insertions, 1 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index fdf56641c..03d00816e 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -1607,12 +1607,14 @@ struct CdPass : public Pass { log("with the specified name in the current module, then this is equivalent\n"); log("to 'cd <celltype>'.\n"); log("\n"); + log("\n"); log(" cd ..\n"); log("\n"); log("Remove trailing substrings that start with '.' in current module name until\n"); log("the name of a module in the current design is generated, then switch to that\n"); log("module. Otherwise clear the current selection.\n"); log("\n"); + log("\n"); log(" cd\n"); log("\n"); log("This is just a shortcut for 'select -clear'.\n"); diff --git a/passes/fsm/fsm.cc b/passes/fsm/fsm.cc index 0c5e624dc..8e7e09d4c 100644 --- a/passes/fsm/fsm.cc +++ b/passes/fsm/fsm.cc @@ -67,6 +67,15 @@ struct FsmPass : public Pass { log(" -encfile file\n"); log(" passed through to fsm_recode pass\n"); log("\n"); + log("This pass uses a subset of FF types to detect FSMs. Run 'opt -nosdff -nodffe'\n"); + log("before this pass to prepare the design.\n"); + log("\n"); +#ifdef YOSYS_ENABLE_VERIFIC + log("The Verific frontend may merge multiplexers in a way that interferes with FSM\n"); + log("detection. Run 'verific -cfg db_infer_wide_muxes_post_elaboration 0' before\n"); + log("reading the source, and 'bmuxmap' after 'proc' for best results.\n"); + log("\n"); +#endif } void execute(std::vector<std::string> args, RTLIL::Design *design) override { diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index f829714c4..5378ec89e 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -272,6 +272,15 @@ struct FsmDetectPass : public Pass { log("Signals can be protected from being detected by this pass by setting the\n"); log("'fsm_encoding' attribute to \"none\".\n"); log("\n"); + log("This pass uses a subset of FF types to detect FSMs. Run 'opt -nosdff -nodffe'\n"); + log("before this pass to prepare the design for fsm_detect.\n"); + log("\n"); +#ifdef YOSYS_ENABLE_VERIFIC + log("The Verific frontend may merge multiplexers in a way that interferes with FSM\n"); + log("detection. Run 'verific -cfg db_infer_wide_muxes_post_elaboration 0' before\n"); + log("reading the source, and 'bmuxmap' after 'proc' for best results.\n"); + log("\n"); +#endif } void execute(std::vector<std::string> args, RTLIL::Design *design) override { diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 3ac431223..1cd1ebc71 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -2014,7 +2014,7 @@ struct SimPass : public Pass { log(" -r\n"); log(" read simulation results file\n"); log(" File formats supported: FST, VCD, AIW and WIT\n"); - log(" VCD support requires vcd2fst external tool to be present\n"); + log(" VCD support requires vcd2fst external tool to be present\n"); log("\n"); log(" -map <filename>\n"); log(" read file with port and latch symbols, needed for AIGER witness input\n"); |