aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/anlogic
diff options
context:
space:
mode:
Diffstat (limited to 'techlibs/anlogic')
-rw-r--r--techlibs/anlogic/.gitignore2
-rw-r--r--techlibs/anlogic/Makefile.inc22
-rw-r--r--techlibs/anlogic/anlogic_eqn.cc2
-rw-r--r--techlibs/anlogic/anlogic_fixcarry.cc2
-rw-r--r--techlibs/anlogic/arith_map.v4
-rw-r--r--techlibs/anlogic/brams.txt43
-rw-r--r--techlibs/anlogic/brams_init.py21
-rw-r--r--techlibs/anlogic/brams_map.v162
-rw-r--r--techlibs/anlogic/cells_map.v38
-rw-r--r--techlibs/anlogic/cells_sim.v45
-rw-r--r--techlibs/anlogic/synth_anlogic.cc25
11 files changed, 309 insertions, 57 deletions
diff --git a/techlibs/anlogic/.gitignore b/techlibs/anlogic/.gitignore
new file mode 100644
index 000000000..d127107db
--- /dev/null
+++ b/techlibs/anlogic/.gitignore
@@ -0,0 +1,2 @@
+brams_init.mk
+brams_init_*.vh
diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc
index 2d8d65e2e..79519c645 100644
--- a/techlibs/anlogic/Makefile.inc
+++ b/techlibs/anlogic/Makefile.inc
@@ -3,6 +3,22 @@ OBJS += techlibs/anlogic/synth_anlogic.o
OBJS += techlibs/anlogic/anlogic_eqn.o
OBJS += techlibs/anlogic/anlogic_fixcarry.o
+GENFILES += techlibs/anlogic/brams_init_16.vh
+GENFILES += techlibs/anlogic/brams_init_9.vh
+GENFILES += techlibs/anlogic/brams_init_8.vh
+
+EXTRA_OBJS += techlibs/anlogic/brams_init.mk
+.SECONDARY: techlibs/anlogic/brams_init.mk
+
+techlibs/anlogic/brams_init.mk: techlibs/anlogic/brams_init.py
+ $(Q) mkdir -p techlibs/anlogic
+ $(P) $(PYTHON_EXECUTABLE) $<
+ $(Q) touch $@
+
+techlibs/anlogic/brams_init_16.vh: techlibs/anlogic/brams_init.mk
+techlibs/anlogic/brams_init_9.vh: techlibs/anlogic/brams_init.mk
+techlibs/anlogic/brams_init_8.vh: techlibs/anlogic/brams_init.mk
+
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
@@ -10,3 +26,9 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams.txt))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams_map.v))
+
+$(eval $(call add_gen_share_file,share/anlogic,techlibs/anlogic/brams_init_16.vh))
+$(eval $(call add_gen_share_file,share/anlogic,techlibs/anlogic/brams_init_9.vh))
+$(eval $(call add_gen_share_file,share/anlogic,techlibs/anlogic/brams_init_8.vh))
diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc
index e5fbc186f..4004b9f17 100644
--- a/techlibs/anlogic/anlogic_eqn.cc
+++ b/techlibs/anlogic/anlogic_eqn.cc
@@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
+ * Copyright (C) 2018 Miodrag Milanovic <micko@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc
index c7dfe3c05..e8d061b93 100644
--- a/techlibs/anlogic/anlogic_fixcarry.cc
+++ b/techlibs/anlogic/anlogic_fixcarry.cc
@@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2019 Miodrag Milanovic <miodrag@symbioticeda.com>
+ * Copyright (C) 2019 Miodrag Milanovic <micko@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v
index 23e190bcb..f0cec4909 100644
--- a/techlibs/anlogic/arith_map.v
+++ b/techlibs/anlogic/arith_map.v
@@ -1,8 +1,8 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Miodrag Milanovic <micko@yosyshq.com>
+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
diff --git a/techlibs/anlogic/brams.txt b/techlibs/anlogic/brams.txt
new file mode 100644
index 000000000..a39701c63
--- /dev/null
+++ b/techlibs/anlogic/brams.txt
@@ -0,0 +1,43 @@
+bram $__ANLOGIC_BRAM9K_TDP
+ init 1
+ abits 13 @a13d1
+ dbits 1 @a13d1
+ abits 12 @a12d2
+ dbits 2 @a12d2
+ abits 11 @a11d4
+ dbits 4 @a11d4
+ abits 10 @a10d9
+ dbits 9 @a10d9
+ groups 2
+ ports 1 1
+ wrmode 0 1
+ enable 1 1
+ transp 2 0
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+bram $__ANLOGIC_BRAM32K
+ init 1
+ abits 11
+ dbits 16
+ groups 2
+ ports 1 1
+ wrmode 0 1
+ enable 1 2
+ transp 0 0
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+match $__ANLOGIC_BRAM32K
+ min efficiency 30
+ shuffle_enable B
+ make_transp
+ or_next_if_better
+endmatch
+
+match $__ANLOGIC_BRAM9K_TDP
+ min efficiency 5
+ make_transp
+endmatch
diff --git a/techlibs/anlogic/brams_init.py b/techlibs/anlogic/brams_init.py
new file mode 100644
index 000000000..8dda0d33e
--- /dev/null
+++ b/techlibs/anlogic/brams_init.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+
+with open("techlibs/anlogic/brams_init_9.vh", "w") as f:
+ for i in range(4):
+ init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
+ for k in range(4, 256, 4):
+ init_snippets[k] = "\n " + init_snippets[k]
+ print(".INITP_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
+ for i in range(32):
+ init_snippets = [" INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)]
+ for k in range(4, 32, 4):
+ init_snippets[k] = "\n " + init_snippets[k]
+ print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
+
+with open("techlibs/anlogic/brams_init_8.vh", "w") as f:
+ for i in range(32):
+ print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
+
+with open("techlibs/anlogic/brams_init_16.vh", "w") as f:
+ for i in range(128):
+ print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
diff --git a/techlibs/anlogic/brams_map.v b/techlibs/anlogic/brams_map.v
new file mode 100644
index 000000000..ee02b6d7c
--- /dev/null
+++ b/techlibs/anlogic/brams_map.v
@@ -0,0 +1,162 @@
+module \$__ANLOGIC_BRAM9K_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+ parameter CFG_ABITS = 10;
+ parameter CFG_DBITS = 9;
+
+ parameter CLKPOL2 = 1;
+ parameter CLKPOL3 = 1;
+ parameter [9215:0] INIT = 9216'bx;
+ parameter TRANSP2 = 0;
+
+ input CLK2;
+ input CLK3;
+
+ input [CFG_ABITS-1:0] A1ADDR;
+ output [CFG_DBITS-1:0] A1DATA;
+ input A1EN;
+
+ input [CFG_ABITS-1:0] B1ADDR;
+ input [CFG_DBITS-1:0] B1DATA;
+ input B1EN;
+
+ localparam CLKAMUX = CLKPOL2 ? "SIG" : "INV";
+ localparam CLKBMUX = CLKPOL3 ? "SIG" : "INV";
+
+ localparam WRITEMODE_B = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
+
+ localparam DATA_WIDTH = CFG_DBITS == 1 ? "1" :
+ (CFG_DBITS == 2 ? "2" :
+ (CFG_DBITS <= 4 ? "4" : "9"));
+
+ localparam APADBITS = $clog2(CFG_DBITS == 9 ? 8 : CFG_DBITS);
+
+ wire [12:0] addra;
+ wire [12:0] addrb;
+
+ assign addra[12:APADBITS] = A1ADDR;
+ assign addrb[12:APADBITS] = B1ADDR;
+
+ wire [8:0] doa;
+ wire [8:0] dib;
+
+ assign A1DATA[CFG_DBITS-1:0] = doa;
+ assign dib[CFG_DBITS-1:0] = B1DATA;
+
+ generate if (CFG_DBITS == 9) begin
+ EG_PHY_BRAM #(
+ .MODE("DP8K"),
+ .DATA_WIDTH_A(DATA_WIDTH),
+ .DATA_WIDTH_B(DATA_WIDTH),
+ .READBACK("OFF"),
+ .REGMODE_A("NOREG"),
+ .REGMODE_B("NOREG"),
+ .WRITEMODE_A("READBEFOREWRITE"),
+ .WRITEMODE_B(WRITEMODE_B),
+ .RESETMODE("ASYNC"),
+ .CEAMUX("SIG"), .CEBMUX("SIG"),
+ .OCEAMUX("1"), .OCEBMUX("1"),
+ .RSTAMUX("0"), .RSTBMUX("0"),
+ .CLKAMUX(CLKAMUX),
+ .CLKBMUX(CLKBMUX),
+ .WEAMUX("0"), .WEBMUX("SIG"),
+ .CSA0("1"), .CSA1("1"),
+ .CSA2("1"), .CSB0("1"),
+ .CSB1("1"), .CSB2("1"),
+ `include "brams_init_9.vh"
+ ) _TECHMAP_REPLACE_ (
+ .doa(doa), .dib(dib),
+ .addra(addra), .addrb(addrb),
+ .clka(CLK2), .clkb(CLK3),
+ .cea(A1EN), .ceb(B1EN),
+ .ocea(1'b1), .oceb(1'b1),
+ .rsta(1'b0), .rstb(1'b0),
+ .wea(1'b0), .web(B1EN),
+ .csa(3'b111), .csb(3'b111)
+ );
+ end else begin
+ EG_PHY_BRAM #(
+ .MODE("DP8K"),
+ .DATA_WIDTH_A(DATA_WIDTH),
+ .DATA_WIDTH_B(DATA_WIDTH),
+ .READBACK("OFF"),
+ .REGMODE_A("NOREG"),
+ .REGMODE_B("NOREG"),
+ .WRITEMODE_A("READBEFOREWRITE"),
+ .WRITEMODE_B(WRITEMODE_B),
+ .RESETMODE("ASYNC"),
+ .CEAMUX("SIG"), .CEBMUX("SIG"),
+ .OCEAMUX("1"), .OCEBMUX("1"),
+ .RSTAMUX("0"), .RSTBMUX("0"),
+ .CLKAMUX(CLKAMUX),
+ .CLKBMUX(CLKBMUX),
+ .WEAMUX("0"), .WEBMUX("SIG"),
+ .CSA0("1"), .CSA1("1"),
+ .CSA2("1"), .CSB0("1"),
+ .CSB1("1"), .CSB2("1"),
+ `include "brams_init_8.vh"
+ ) _TECHMAP_REPLACE_ (
+ .doa(doa), .dib(dib),
+ .addra(addra), .addrb(addrb),
+ .clka(CLK2), .clkb(CLK3),
+ .cea(A1EN), .ceb(B1EN),
+ .ocea(1'b1), .oceb(1'b1),
+ .rsta(1'b0), .rstb(1'b0),
+ .wea(1'b0), .web(B1EN),
+ .csa(3'b111), .csb(3'b111)
+ );
+ end endgenerate
+endmodule
+
+module \$__ANLOGIC_BRAM32K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+ parameter CFG_ABITS = 11;
+ parameter CFG_DBITS = 16;
+
+ parameter CLKPOL2 = 1;
+ parameter CLKPOL3 = 1;
+ parameter [32767:0] INIT = 32768'bx;
+
+ input CLK2;
+ input CLK3;
+
+ input [CFG_ABITS-1:0] A1ADDR;
+ output [CFG_DBITS-1:0] A1DATA;
+ input A1EN;
+
+ input [CFG_ABITS-1:0] B1ADDR;
+ input [CFG_DBITS-1:0] B1DATA;
+ input [1:0] B1EN;
+
+ localparam CLKAMUX = CLKPOL2 ? "SIG" : "INV";
+ localparam CLKBMUX = CLKPOL3 ? "SIG" : "INV";
+
+ wire byteweb = B1EN[1] ^ B1EN[0];
+ wire byteb = B1EN[1];
+
+ EG_PHY_BRAM32K #(
+ .MODE("DP16K"),
+ .DATA_WIDTH_A("16"),
+ .DATA_WIDTH_B("16"),
+ .REGMODE_A("NOREG"),
+ .REGMODE_B("NOREG"),
+ .WRITEMODE_A("NORMAL"),
+ .WRITEMODE_B("NORMAL"),
+ .SRMODE("ASYNC"),
+ .CSAMUX("SIG"), .CSBMUX("SIG"),
+ .OCEAMUX("1"), .OCEBMUX("1"),
+ .RSTAMUX("0"), .RSTBMUX("0"),
+ .CLKAMUX(CLKAMUX),
+ .CLKBMUX(CLKBMUX),
+ .WEAMUX("0"), .WEBMUX("SIG"),
+ .READBACK("OFF"),
+ `include "brams_init_16.vh"
+ ) _TECHMAP_REPLACE_ (
+ .doa(A1DATA), .dib(B1DATA),
+ .addra(A1ADDR), .addrb(B1ADDR),
+ .bytea(1'b0), .byteb(byteb),
+ .bytewea(1'b0), .byteweb(byteweb),
+ .csa(A1EN), .csb(|B1EN),
+ .wea(1'b0), .web(|B1EN),
+ .clka(CLK2), .clkb(CLK3),
+ .rsta(1'b0), .rstb(1'b0),
+ .ocea(1'b1), .oceb(1'b1)
+ );
+endmodule
diff --git a/techlibs/anlogic/cells_map.v b/techlibs/anlogic/cells_map.v
index 0bcea9856..d9f264ab1 100644
--- a/techlibs/anlogic/cells_map.v
+++ b/techlibs/anlogic/cells_map.v
@@ -1,31 +1,17 @@
-module \$_DFF_N_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(1'b0)); endmodule
-module \$_DFF_P_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(1'b0)); endmodule
+module \$_DFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_DFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_DFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_DFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
-module \$_DFFE_NN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
-module \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
-module \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
-module \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule
+module \$_SDFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_SDFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_SDFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_SDFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
-module \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
-module \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule
-
-module \$_DLATCH_N_ (E, D, Q);
- wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
- input E, D;
- output Q = !E ? D : Q;
-endmodule
-
-module \$_DLATCH_P_ (E, D, Q);
- wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
- input E, D;
- output Q = E ? D : Q;
-endmodule
+module \$_DLATCH_NN0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E) ,.ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_DLATCH_NN1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_DLATCH_NP0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
+module \$_DLATCH_NP1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
`ifndef NO_LUT
module \$lut (A, Y);
diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v
index 0fba43572..e8ecf4f03 100644
--- a/techlibs/anlogic/cells_sim.v
+++ b/techlibs/anlogic/cells_sim.v
@@ -10,9 +10,6 @@ module AL_MAP_SEQ (
parameter SRMUX = "SR"; //SR/INV
parameter SRMODE = "SYNC"; //SYNC/ASYNC
- wire clk_ce;
- assign clk_ce = ce ? clk : 1'b0;
-
wire srmux;
generate
case (SRMUX)
@@ -20,7 +17,7 @@ module AL_MAP_SEQ (
"INV": assign srmux = ~sr;
default: assign srmux = sr;
endcase
- endgenerate
+ endgenerate
wire regset;
generate
@@ -34,43 +31,45 @@ module AL_MAP_SEQ (
initial q = regset;
generate
- if (DFFMODE == "FF")
+ if (DFFMODE == "FF")
begin
- if (SRMODE == "ASYNC")
+ if (SRMODE == "ASYNC")
begin
- always @(posedge clk_ce, posedge srmux)
+ always @(posedge clk, posedge srmux)
if (srmux)
q <= regset;
- else
- q <= d;
- end
+ else if (ce)
+ q <= d;
+ end
else
begin
- always @(posedge clk_ce)
+ always @(posedge clk)
if (srmux)
q <= regset;
- else
- q <= d;
+ else if (ce)
+ q <= d;
end
end
else
begin
// DFFMODE == "LATCH"
- if (SRMODE == "ASYNC")
+ if (SRMODE == "ASYNC")
begin
- always @(clk_ce, srmux)
+ always @*
if (srmux)
q <= regset;
- else
- q <= d;
- end
+ else if (~clk & ce)
+ q <= d;
+ end
else
begin
- always @(clk_ce)
- if (srmux)
- q <= regset;
- else
- q <= d;
+ always @*
+ if (~clk) begin
+ if (srmux)
+ q <= regset;
+ else if (ce)
+ q <= d;
+ end
end
end
endgenerate
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index d7475df86..5da14c26b 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -1,8 +1,8 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
- * Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Miodrag Milanovic <micko@yosyshq.com>
+ * Copyright (C) 2018 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -63,6 +63,9 @@ struct SynthAnlogicPass : public ScriptPass
log(" -nolutram\n");
log(" do not use EG_LOGIC_DRAM16X4 cells in output netlist\n");
log("\n");
+ log(" -nobram\n");
+ log(" do not use EG_PHY_BRAM or EG_PHY_BRAM32K cells in output netlist\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
@@ -70,7 +73,7 @@ struct SynthAnlogicPass : public ScriptPass
}
string top_opt, edif_file, json_file;
- bool flatten, retime, nolutram;
+ bool flatten, retime, nolutram, nobram;
void clear_flags() override
{
@@ -80,6 +83,7 @@ struct SynthAnlogicPass : public ScriptPass
flatten = true;
retime = false;
nolutram = false;
+ nobram = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -118,6 +122,10 @@ struct SynthAnlogicPass : public ScriptPass
nolutram = true;
continue;
}
+ if (args[argidx] == "-nobram") {
+ nobram = true;
+ continue;
+ }
if (args[argidx] == "-retime") {
retime = true;
continue;
@@ -158,6 +166,14 @@ struct SynthAnlogicPass : public ScriptPass
run("synth -run coarse");
}
+ if (!nobram && check_label("map_bram", "(skip if -nobram)"))
+ {
+ run("memory_bram -rules +/anlogic/brams.txt");
+ run("techmap -map +/anlogic/brams_map.v");
+ run("setundef -zero -params t:EG_PHY_BRAM");
+ run("setundef -zero -params t:EG_PHY_BRAM32K");
+ }
+
if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
{
run("memory_bram -rules +/anlogic/lutrams.txt");
@@ -182,8 +198,8 @@ struct SynthAnlogicPass : public ScriptPass
if (check_label("map_ffs"))
{
+ run("dfflegalize -cell $_DFFE_P??P_ r -cell $_SDFFE_P??P_ r -cell $_DLATCH_N??_ r");
run("techmap -D NO_LUT -map +/anlogic/cells_map.v");
- run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit");
run("opt_expr -mux_undef");
run("simplemap");
}
@@ -211,6 +227,7 @@ struct SynthAnlogicPass : public ScriptPass
run("hierarchy -check");
run("stat");
run("check -noinit");
+ run("blackbox =A:whitebox");
}
if (check_label("edif"))
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-09 03:04:18 +0000