aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/common/simcells.v
diff options
context:
space:
mode:
Diffstat (limited to 'techlibs/common/simcells.v')
-rw-r--r--techlibs/common/simcells.v86
1 files changed, 47 insertions, 39 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 64720e598..157e8d23b 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -456,23 +456,27 @@ output Y;
assign Y = E ? A : 1'bz;
endmodule
+// NOTE: the following cell types are autogenerated. DO NOT EDIT them manually,
+// instead edit the templates in gen_ff_types.py and rerun it.
+
+// START AUTOGENERATED CELL TYPES
+
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SR_NN_ (S, R, Q)
//-
-//- A set-reset latch with negative polarity SET and RESET.
+//- A set-reset latch with negative polarity SET and negative polarity RESET.
//-
//- Truth table: S R | Q
//- -----+---
-//- 0 0 | x
-//- 0 1 | 1
-//- 1 0 | 0
-//- 1 1 | y
+//- - 0 | 0
+//- 0 - | 1
+//- - - | q
//-
module \$_SR_NN_ (S, R, Q);
input S, R;
output reg Q;
-always @(negedge S, negedge R) begin
+always @* begin
if (R == 0)
Q <= 0;
else if (S == 0)
@@ -488,15 +492,14 @@ endmodule
//-
//- Truth table: S R | Q
//- -----+---
-//- 0 1 | x
-//- 0 0 | 1
-//- 1 1 | 0
-//- 1 0 | y
+//- - 1 | 0
+//- 0 - | 1
+//- - - | q
//-
module \$_SR_NP_ (S, R, Q);
input S, R;
output reg Q;
-always @(negedge S, posedge R) begin
+always @* begin
if (R == 1)
Q <= 0;
else if (S == 0)
@@ -512,15 +515,14 @@ endmodule
//-
//- Truth table: S R | Q
//- -----+---
-//- 1 0 | x
-//- 1 1 | 1
-//- 0 0 | 0
-//- 0 1 | y
+//- - 0 | 0
+//- 1 - | 1
+//- - - | q
//-
module \$_SR_PN_ (S, R, Q);
input S, R;
output reg Q;
-always @(posedge S, negedge R) begin
+always @* begin
if (R == 0)
Q <= 0;
else if (S == 1)
@@ -532,19 +534,18 @@ endmodule
//-
//- $_SR_PP_ (S, R, Q)
//-
-//- A set-reset latch with positive polarity SET and RESET.
+//- A set-reset latch with positive polarity SET and positive polarity RESET.
//-
//- Truth table: S R | Q
//- -----+---
-//- 1 1 | x
-//- 1 0 | 1
-//- 0 1 | 0
-//- 0 0 | y
+//- - 1 | 0
+//- 1 - | 1
+//- - - | q
//-
module \$_SR_PP_ (S, R, Q);
input S, R;
output reg Q;
-always @(posedge S, posedge R) begin
+always @* begin
if (R == 1)
Q <= 0;
else if (S == 1)
@@ -871,7 +872,8 @@ endmodule
//-
//- $_DFFSR_NNN_ (C, S, R, D, Q)
//-
-//- A negative edge D-type flip-flop with negative polarity set and reset.
+//- A negative edge D-type flip-flop with negative polarity set and negative
+//- polarity reset.
//-
//- Truth table: C S R D | Q
//- ---------+---
@@ -951,7 +953,8 @@ endmodule
//-
//- $_DFFSR_NPP_ (C, S, R, D, Q)
//-
-//- A negative edge D-type flip-flop with positive polarity set and reset.
+//- A negative edge D-type flip-flop with positive polarity set and positive
+//- polarity reset.
//-
//- Truth table: C S R D | Q
//- ---------+---
@@ -977,7 +980,8 @@ endmodule
//-
//- $_DFFSR_PNN_ (C, S, R, D, Q)
//-
-//- A positive edge D-type flip-flop with negative polarity set and reset.
+//- A positive edge D-type flip-flop with negative polarity set and negative
+//- polarity reset.
//-
//- Truth table: C S R D | Q
//- ---------+---
@@ -1057,7 +1061,8 @@ endmodule
//-
//- $_DFFSR_PPP_ (C, S, R, D, Q)
//-
-//- A positive edge D-type flip-flop with positive polarity set and reset.
+//- A positive edge D-type flip-flop with positive polarity set and positive
+//- polarity reset.
//-
//- Truth table: C S R D | Q
//- ---------+---
@@ -1123,7 +1128,8 @@ endmodule
//-
//- $_DLATCHSR_NNN_ (E, S, R, D, Q)
//-
-//- A negative enable D-type latch with negative polarity set and reset.
+//- A negative enable D-type latch with negative polarity set and negative
+//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
@@ -1149,8 +1155,8 @@ endmodule
//-
//- $_DLATCHSR_NNP_ (E, S, R, D, Q)
//-
-//- A negative enable D-type latch with negative polarity set and positive polarity
-//- reset.
+//- A negative enable D-type latch with negative polarity set and positive
+//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
@@ -1176,8 +1182,8 @@ endmodule
//-
//- $_DLATCHSR_NPN_ (E, S, R, D, Q)
//-
-//- A negative enable D-type latch with positive polarity set and negative polarity
-//- reset.
+//- A negative enable D-type latch with positive polarity set and negative
+//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
@@ -1203,7 +1209,8 @@ endmodule
//-
//- $_DLATCHSR_NPP_ (E, S, R, D, Q)
//-
-//- A negative enable D-type latch with positive polarity set and reset.
+//- A negative enable D-type latch with positive polarity set and positive
+//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
@@ -1229,7 +1236,8 @@ endmodule
//-
//- $_DLATCHSR_PNN_ (E, S, R, D, Q)
//-
-//- A positive enable D-type latch with negative polarity set and reset.
+//- A positive enable D-type latch with negative polarity set and negative
+//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
@@ -1255,8 +1263,8 @@ endmodule
//-
//- $_DLATCHSR_PNP_ (E, S, R, D, Q)
//-
-//- A positive enable D-type latch with negative polarity set and positive polarity
-//- reset.
+//- A positive enable D-type latch with negative polarity set and positive
+//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
@@ -1282,8 +1290,8 @@ endmodule
//-
//- $_DLATCHSR_PPN_ (E, S, R, D, Q)
//-
-//- A positive enable D-type latch with positive polarity set and negative polarity
-//- reset.
+//- A positive enable D-type latch with positive polarity set and negative
+//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
@@ -1309,7 +1317,8 @@ endmodule
//-
//- $_DLATCHSR_PPP_ (E, S, R, D, Q)
//-
-//- A positive enable D-type latch with positive polarity set and reset.
+//- A positive enable D-type latch with positive polarity set and positive
+//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
@@ -1330,4 +1339,3 @@ always @* begin
Q <= D;
end
endmodule
-
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-02 21:22:14 +0000