diff options
Diffstat (limited to 'techlibs/common/simcells.v')
| -rw-r--r-- | techlibs/common/simcells.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 669706209..9a820f71c 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -19,7 +19,7 @@ * * The internal logic cell simulation library. * - * This verilog library contains simple simulation models for the internal + * This Verilog library contains simple simulation models for the internal * logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology * mapper (see "techmap.v" in this directory) and expected by the "abc" pass. * |