diff options
Diffstat (limited to 'techlibs/common/simcells.v')
| -rw-r--r-- | techlibs/common/simcells.v | 152 |
1 files changed, 149 insertions, 3 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 10a809db6..a2a377350 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -20,12 +20,12 @@ * The internal logic cell simulation library. * * This verilog library contains simple simulation models for the internal - * logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology - * mapper (see "stdcells.v" in this directory) and expected by the "abc" pass. + * logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology + * mapper (see "techmap.v" in this directory) and expected by the "abc" pass. * */ -module \$_INV_ (A, Y); +module \$_NOT_ (A, Y); input A; output Y; assign Y = ~A; @@ -37,24 +37,66 @@ output Y; assign Y = A & B; endmodule +module \$_NAND_ (A, B, Y); +input A, B; +output Y; +assign Y = ~(A & B); +endmodule + module \$_OR_ (A, B, Y); input A, B; output Y; assign Y = A | B; endmodule +module \$_NOR_ (A, B, Y); +input A, B; +output Y; +assign Y = ~(A | B); +endmodule + module \$_XOR_ (A, B, Y); input A, B; output Y; assign Y = A ^ B; endmodule +module \$_XNOR_ (A, B, Y); +input A, B; +output Y; +assign Y = ~(A ^ B); +endmodule + module \$_MUX_ (A, B, S, Y); input A, B, S; output Y; assign Y = S ? B : A; endmodule +module \$_AOI3_ (A, B, C, Y); +input A, B, C; +output Y; +assign Y = ~((A & B) | C); +endmodule + +module \$_OAI3_ (A, B, C, Y); +input A, B, C; +output Y; +assign Y = ~((A | B) & C); +endmodule + +module \$_AOI4_ (A, B, C, D, Y); +input A, B, C, D; +output Y; +assign Y = ~((A & B) | (C & D)); +endmodule + +module \$_OAI4_ (A, B, C, D, Y); +input A, B, C, D; +output Y; +assign Y = ~((A | B) & (C | D)); +endmodule + module \$_SR_NN_ (S, R, Q); input S, R; output reg Q; @@ -325,3 +367,107 @@ always @* begin end endmodule +module \$_DLATCHSR_NNN_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 0) + Q <= 0; + else if (S == 0) + Q <= 1; + else if (E == 0) + Q <= D; +end +endmodule + +module \$_DLATCHSR_NNP_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 1) + Q <= 0; + else if (S == 0) + Q <= 1; + else if (E == 0) + Q <= D; +end +endmodule + +module \$_DLATCHSR_NPN_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 0) + Q <= 0; + else if (S == 1) + Q <= 1; + else if (E == 0) + Q <= D; +end +endmodule + +module \$_DLATCHSR_NPP_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 1) + Q <= 0; + else if (S == 1) + Q <= 1; + else if (E == 0) + Q <= D; +end +endmodule + +module \$_DLATCHSR_PNN_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 0) + Q <= 0; + else if (S == 0) + Q <= 1; + else if (E == 1) + Q <= D; +end +endmodule + +module \$_DLATCHSR_PNP_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 1) + Q <= 0; + else if (S == 0) + Q <= 1; + else if (E == 1) + Q <= D; +end +endmodule + +module \$_DLATCHSR_PPN_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 0) + Q <= 0; + else if (S == 1) + Q <= 1; + else if (E == 1) + Q <= D; +end +endmodule + +module \$_DLATCHSR_PPP_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 1) + Q <= 0; + else if (S == 1) + Q <= 1; + else if (E == 1) + Q <= D; +end +endmodule + |