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-rw-r--r--techlibs/common/techmap.v145
1 files changed, 76 insertions, 69 deletions
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 9607302b7..91d385b80 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -59,12 +59,12 @@ module _90_simplemap_compare_ops;
endmodule
(* techmap_simplemap *)
-(* techmap_celltype = "$pos $slice $concat $mux $tribuf" *)
+(* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux" *)
module _90_simplemap_various;
endmodule
(* techmap_simplemap *)
-(* techmap_celltype = "$sr $ff $dff $dffe $adff $adffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr" *)
+(* techmap_celltype = "$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr" *)
module _90_simplemap_registers;
endmodule
@@ -141,78 +141,48 @@ module _90_shift_shiftx (A, B, Y);
parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
+ wire a_padding = _TECHMAP_CELLTYPE_ == "$shiftx" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);
- generate
-`ifndef NO_LSB_FIRST_SHIFT_SHIFTX
- // If $shift/$shiftx only shifts in units of Y_WIDTH
- // (a common pattern created by pmux2shiftx)
- // which is checked by ensuring that all that
- // the appropriate LSBs of B are constant zero,
- // then we can decompose LSB first instead of
- // MSB first
- localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH);
- if (B_WIDTH > CLOG2_Y_WIDTH+1 &&
- _TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} &&
- _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin
- // Halve the size of $shift/$shiftx by $mux-ing A according to
- // the LSB of B, after discarding the zeroed bits
- localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
- localparam entries = (A_WIDTH+Y_WIDTH-1)/Y_WIDTH2;
- localparam len = Y_WIDTH2 * ((entries+1)/2);
- wire [len-1:0] AA;
- wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){extbit}}, A};
- genvar i;
- for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2)
- assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? Apad[i+Y_WIDTH2 +: Y_WIDTH2] : Apad[i +: Y_WIDTH2];
- wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
- if (_TECHMAP_CELLTYPE_ == "$shift")
- $shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
- else
- $shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
- end
- else
-`endif
- begin
- localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
- localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
+ localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
+ localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
- wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
- wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
+ wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
+ wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
- integer i;
- (* force_downto *)
- reg [WIDTH-1:0] buffer;
- reg overflow;
+ integer i;
+ (* force_downto *)
+ reg [WIDTH-1:0] buffer;
+ reg overflow;
- always @* begin
- overflow = 0;
+ always @* begin
+ overflow = 0;
+ buffer = {WIDTH{extbit}};
+ buffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};
+ buffer[A_WIDTH-1:0] = A;
+
+ if (B_WIDTH > BB_WIDTH) begin
+ if (B_SIGNED) begin
+ for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
+ if (B[i] != B[BB_WIDTH-1])
+ overflow = 1;
+ end else
+ overflow = |B[B_WIDTH-1:BB_WIDTH];
+ if (overflow)
buffer = {WIDTH{extbit}};
- buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
-
- if (B_WIDTH > BB_WIDTH) begin
- if (B_SIGNED) begin
- for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
- if (B[i] != B[BB_WIDTH-1])
- overflow = 1;
- end else
- overflow = |B[B_WIDTH-1:BB_WIDTH];
- if (overflow)
- buffer = {WIDTH{extbit}};
- end
-
- for (i = BB_WIDTH-1; i >= 0; i = i-1)
- if (B[i]) begin
- if (B_SIGNED && i == BB_WIDTH-1)
- buffer = {buffer, {2**i{extbit}}};
- else if (2**i < WIDTH)
- buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
- else
- buffer = {WIDTH{extbit}};
- end
- end
- assign Y = buffer;
end
- endgenerate
+
+ if (B_SIGNED && B[BB_WIDTH-1])
+ buffer = {buffer, {2**(BB_WIDTH-1){extbit}}};
+
+ for (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)
+ if (B[i]) begin
+ if (2**i < WIDTH)
+ buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
+ else
+ buffer = {WIDTH{extbit}};
+ end
+ end
+ assign Y = buffer;
endmodule
@@ -627,6 +597,43 @@ module _90_pmux (A, B, S, Y);
assign Y = |S ? Y_B : A;
endmodule
+// --------------------------------------------------------
+// Demultiplexers
+// --------------------------------------------------------
+
+(* techmap_celltype = "$demux" *)
+module _90_demux (A, S, Y);
+ parameter WIDTH = 1;
+ parameter S_WIDTH = 1;
+
+ (* force_downto *)
+ input [WIDTH-1:0] A;
+ (* force_downto *)
+ input [S_WIDTH-1:0] S;
+ (* force_downto *)
+ output [(WIDTH << S_WIDTH)-1:0] Y;
+
+ generate
+ if (S_WIDTH == 0) begin
+ assign Y = A;
+ end else if (S_WIDTH == 1) begin
+ assign Y[0+:WIDTH] = S ? 0 : A;
+ assign Y[WIDTH+:WIDTH] = S ? A : 0;
+ end else begin
+ localparam SPLIT = S_WIDTH / 2;
+ wire [(1 << (S_WIDTH-SPLIT))-1:0] YH;
+ wire [(1 << SPLIT)-1:0] YL;
+ $demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL));
+ $demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH));
+ genvar i;
+ for (i = 0; i < (1 << S_WIDTH); i = i + 1) begin
+ localparam [S_WIDTH-1:0] IDX = i;
+ assign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0;
+ end
+ end
+ endgenerate
+endmodule
+
// --------------------------------------------------------
// LUTs
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 23:54:27 +0000