diff options
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/Makefile.inc | 1 | ||||
| -rw-r--r-- | techlibs/common/abc9_model.v | 10 | ||||
| -rw-r--r-- | techlibs/common/gate2lut.v | 2 | ||||
| -rw-r--r-- | techlibs/common/synth.cc | 19 | ||||
| -rw-r--r-- | techlibs/common/techmap.v | 14 |
5 files changed, 35 insertions, 11 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index 42f1068ad..d5e69a241 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -29,3 +29,4 @@ $(eval $(call add_share_file,share,techlibs/common/gate2lut.v)) $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v)) $(eval $(call add_share_file,share,techlibs/common/cells.lib)) $(eval $(call add_share_file,share,techlibs/common/mul2dsp.v)) +$(eval $(call add_share_file,share,techlibs/common/abc9_model.v)) diff --git a/techlibs/common/abc9_model.v b/techlibs/common/abc9_model.v new file mode 100644 index 000000000..c0c5dc2fd --- /dev/null +++ b/techlibs/common/abc9_model.v @@ -0,0 +1,10 @@ +module \$__ABC9_FF_ (input D, output Q); +endmodule + +(* abc9_box *) +module \$__ABC9_DELAY (input I, output O); + parameter DELAY = 0; + specify + (I => O) = DELAY; + endspecify +endmodule diff --git a/techlibs/common/gate2lut.v b/techlibs/common/gate2lut.v index 99c123f4a..15cea3d8d 100644 --- a/techlibs/common/gate2lut.v +++ b/techlibs/common/gate2lut.v @@ -79,7 +79,7 @@ module _90_lut_mux (A, B, S, Y); // A 1010 1010 // B 1100 1100 // S 1111 0000 - .LUT(8'b_1100_1010) + .LUT(8'b 1100_1010) ) lut ( .A(AA), .Y(Y) diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index a176357a7..e7a192c07 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -78,6 +78,9 @@ struct SynthPass : public ScriptPass log(" -abc9\n"); log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); + log(" -flowmap\n"); + log(" use FlowMap LUT techmapping instead of ABC\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -85,7 +88,7 @@ struct SynthPass : public ScriptPass } string top_module, fsm_opts, memory_opts, abc; - bool autotop, flatten, noalumacc, nofsm, noabc, noshare; + bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap; int lut; void clear_flags() YS_OVERRIDE @@ -101,6 +104,7 @@ struct SynthPass : public ScriptPass nofsm = false; noabc = false; noshare = false; + flowmap = false; abc = "abc"; } @@ -167,6 +171,10 @@ struct SynthPass : public ScriptPass abc = "abc9"; continue; } + if (args[argidx] == "-flowmap") { + flowmap = true; + continue; + } break; } extra_args(args, argidx, design); @@ -176,6 +184,8 @@ struct SynthPass : public ScriptPass if (abc == "abc9" && !lut) log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n"); + if (flowmap && !lut) + log_cmd_error("FlowMap is only supported for FPGA synthesis (using '-lut' option)\n"); log_header(design, "Executing SYNTH pass.\n"); log_push(); @@ -240,15 +250,20 @@ struct SynthPass : public ScriptPass { run("techmap -map +/gate2lut.v", "(if -noabc and -lut)"); run("clean; opt_lut", " (if -noabc and -lut)"); + run("flowmap -maxlut K", " (if -flowmap and -lut)"); } else if (noabc && lut) { run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut)); run("clean; opt_lut"); } + else if (flowmap) + { + run(stringf("flowmap -maxlut %d", lut)); + } run("opt -fast"); - if (!noabc) { + if (!noabc && !flowmap) { #ifdef YOSYS_ENABLE_ABC if (help_mode) { diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index be6530eb4..ecf4d5dc5 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -149,16 +149,14 @@ module _90_shift_shiftx (A, B, Y); _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin // Halve the size of $shift/$shiftx by $mux-ing A according to // the LSB of B, after discarding the zeroed bits - localparam len = 2**(B_WIDTH-1); localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH; - wire [len-1:0] T, F, AA; - wire [(A_WIDTH+Y_WIDTH2*2):0] Apad = {{Y_WIDTH2*2{extbit}}, A}; + localparam entries = (A_WIDTH+Y_WIDTH-1)/Y_WIDTH2; + localparam len = Y_WIDTH2 * ((entries+1)/2); + wire [len-1:0] AA; + wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){extbit}}, A}; genvar i; - for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin - assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2]; - assign T[i/2 +: Y_WIDTH2] = Apad[i+Y_WIDTH2 +: Y_WIDTH2]; - assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? T[i/2 +: Y_WIDTH2] : F[i/2 +: Y_WIDTH2]; - end + for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) + assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? Apad[i+Y_WIDTH2 +: Y_WIDTH2] : Apad[i +: Y_WIDTH2]; wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}; if (_TECHMAP_CELLTYPE_ == "$shift") $shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y)); |