diff options
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/Makefile.inc | 1 | ||||
| -rw-r--r-- | techlibs/common/abc9_model.v | 10 | ||||
| -rw-r--r-- | techlibs/common/techmap.v | 13 |
3 files changed, 17 insertions, 7 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index 42f1068ad..d5e69a241 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -29,3 +29,4 @@ $(eval $(call add_share_file,share,techlibs/common/gate2lut.v)) $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v)) $(eval $(call add_share_file,share,techlibs/common/cells.lib)) $(eval $(call add_share_file,share,techlibs/common/mul2dsp.v)) +$(eval $(call add_share_file,share,techlibs/common/abc9_model.v)) diff --git a/techlibs/common/abc9_model.v b/techlibs/common/abc9_model.v new file mode 100644 index 000000000..c0c5dc2fd --- /dev/null +++ b/techlibs/common/abc9_model.v @@ -0,0 +1,10 @@ +module \$__ABC9_FF_ (input D, output Q); +endmodule + +(* abc9_box *) +module \$__ABC9_DELAY (input I, output O); + parameter DELAY = 0; + specify + (I => O) = DELAY; + endspecify +endmodule diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 75a51e55e..ecf4d5dc5 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -149,15 +149,14 @@ module _90_shift_shiftx (A, B, Y); _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin // Halve the size of $shift/$shiftx by $mux-ing A according to // the LSB of B, after discarding the zeroed bits - localparam len = 2**(B_WIDTH-1); localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH; - wire [len-1:0] T, F, AA; + localparam entries = (A_WIDTH+Y_WIDTH-1)/Y_WIDTH2; + localparam len = Y_WIDTH2 * ((entries+1)/2); + wire [len-1:0] AA; + wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){extbit}}, A}; genvar i; - for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin - assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2]; - assign T[i/2 +: Y_WIDTH2] = (i + Y_WIDTH2 < A_WIDTH) ? A[i+Y_WIDTH2 +: Y_WIDTH2] : {Y_WIDTH2{extbit}}; - assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? T[i/2 +: Y_WIDTH2] : F[i/2 +: Y_WIDTH2]; - end + for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) + assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? Apad[i+Y_WIDTH2 +: Y_WIDTH2] : Apad[i +: Y_WIDTH2]; wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}; if (_TECHMAP_CELLTYPE_ == "$shift") $shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y)); |