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-rw-r--r--techlibs/common/Makefile.inc34
-rw-r--r--techlibs/common/cells.lib108
-rw-r--r--techlibs/common/simcells.v38
-rw-r--r--techlibs/common/simlib.v238
-rw-r--r--techlibs/common/synth.cc54
-rw-r--r--techlibs/common/techmap.v58
6 files changed, 348 insertions, 182 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 7c8cc2f66..d2ce61cf6 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -1,5 +1,7 @@
+ifneq ($(SMALL),1)
OBJS += techlibs/common/synth.o
+endif
EXTRA_TARGETS += techlibs/common/blackbox.v
@@ -7,29 +9,11 @@ techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.
$(P) cat techlibs/common/simlib.v techlibs/common/simcells.v | $(SED) -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
$(Q) mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v
-EXTRA_TARGETS += share/simlib.v share/simcells.v share/techmap.v share/blackbox.v share/pmux2mux.v share/adff2dff.v
-
-share/simlib.v: techlibs/common/simlib.v
- $(P) mkdir -p share
- $(Q) cp techlibs/common/simlib.v share/simlib.v
-
-share/simcells.v: techlibs/common/simcells.v
- $(P) mkdir -p share
- $(Q) cp techlibs/common/simcells.v share/simcells.v
-
-share/techmap.v: techlibs/common/techmap.v
- $(P) mkdir -p share
- $(Q) cp techlibs/common/techmap.v share/techmap.v
-
-share/blackbox.v: techlibs/common/blackbox.v
- $(P) mkdir -p share
- $(Q) cp techlibs/common/blackbox.v share/blackbox.v
-
-share/pmux2mux.v: techlibs/common/pmux2mux.v
- $(P) mkdir -p share
- $(Q) cp techlibs/common/pmux2mux.v share/pmux2mux.v
-
-share/adff2dff.v: techlibs/common/adff2dff.v
- $(P) mkdir -p share
- $(Q) cp techlibs/common/adff2dff.v share/adff2dff.v
+$(eval $(call add_share_file,share,techlibs/common/simlib.v))
+$(eval $(call add_share_file,share,techlibs/common/simcells.v))
+$(eval $(call add_share_file,share,techlibs/common/techmap.v))
+$(eval $(call add_share_file,share,techlibs/common/blackbox.v))
+$(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
+$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
+$(eval $(call add_share_file,share,techlibs/common/cells.lib))
diff --git a/techlibs/common/cells.lib b/techlibs/common/cells.lib
new file mode 100644
index 000000000..eb89036d7
--- /dev/null
+++ b/techlibs/common/cells.lib
@@ -0,0 +1,108 @@
+library(yosys_cells) {
+ cell(DFF_N) {
+ ff(IQ, IQN) {
+ clocked_on: "!C";
+ next_state: "D";
+ }
+ pin(D) { direction: input; }
+ pin(C) { direction: input; clock: true; }
+ pin(Q) { direction: output; function: "IQ"; }
+ }
+ cell(DFF_P) {
+ ff(IQ, IQN) {
+ clocked_on: "C";
+ next_state: "D";
+ }
+ pin(D) { direction: input; }
+ pin(C) { direction: input; clock: true; }
+ pin(Q) { direction: output; function: "IQ"; }
+ }
+ cell(DFF_NN0) {
+ ff(IQ, IQN) {
+ clocked_on: "!C";
+ next_state: "D";
+ clear: "!R";
+ }
+ pin(D) { direction: input; }
+ pin(R) { direction: input; }
+ pin(C) { direction: input; clock: true; }
+ pin(Q) { direction: output; function: "IQ"; }
+ }
+ cell(DFF_NN1) {
+ ff(IQ, IQN) {
+ clocked_on: "!C";
+ next_state: "D";
+ preset: "!R";
+ }
+ pin(D) { direction: input; }
+ pin(R) { direction: input; }
+ pin(C) { direction: input; clock: true; }
+ pin(Q) { direction: output; function: "IQ"; }
+ }
+ cell(DFF_NP0) {
+ ff(IQ, IQN) {
+ clocked_on: "!C";
+ next_state: "D";
+ clear: "R";
+ }
+ pin(D) { direction: input; }
+ pin(R) { direction: input; }
+ pin(C) { direction: input; clock: true; }
+ pin(Q) { direction: output; function: "IQ"; }
+ }
+ cell(DFF_NP1) {
+ ff(IQ, IQN) {
+ clocked_on: "!C";
+ next_state: "D";
+ preset: "R";
+ }
+ pin(D) { direction: input; }
+ pin(R) { direction: input; }
+ pin(C) { direction: input; clock: true; }
+ pin(Q) { direction: output; function: "IQ"; }
+ }
+ cell(DFF_PN0) {
+ ff(IQ, IQN) {
+ clocked_on: "C";
+ next_state: "D";
+ clear: "!R";
+ }
+ pin(D) { direction: input; }
+ pin(R) { direction: input; }
+ pin(C) { direction: input; clock: true; }
+ pin(Q) { direction: output; function: "IQ"; }
+ }
+ cell(DFF_PN1) {
+ ff(IQ, IQN) {
+ clocked_on: "C";
+ next_state: "D";
+ preset: "!R";
+ }
+ pin(D) { direction: input; }
+ pin(R) { direction: input; }
+ pin(C) { direction: input; clock: true; }
+ pin(Q) { direction: output; function: "IQ"; }
+ }
+ cell(DFF_PP0) {
+ ff(IQ, IQN) {
+ clocked_on: "C";
+ next_state: "D";
+ clear: "R";
+ }
+ pin(D) { direction: input; }
+ pin(R) { direction: input; }
+ pin(C) { direction: input; clock: true; }
+ pin(Q) { direction: output; function: "IQ"; }
+ }
+ cell(DFF_PP1) {
+ ff(IQ, IQN) {
+ clocked_on: "C";
+ next_state: "D";
+ preset: "R";
+ }
+ pin(D) { direction: input; }
+ pin(R) { direction: input; }
+ pin(C) { direction: input; clock: true; }
+ pin(Q) { direction: output; function: "IQ"; }
+ }
+}
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index a2a377350..eb62d7830 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -25,6 +25,12 @@
*
*/
+module \$_BUF_ (A, Y);
+input A;
+output Y;
+assign Y = A;
+endmodule
+
module \$_NOT_ (A, Y);
input A;
output Y;
@@ -157,6 +163,38 @@ always @(posedge C) begin
end
endmodule
+module \$_DFFE_NN_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(negedge C) begin
+ if (!E) Q <= D;
+end
+endmodule
+
+module \$_DFFE_NP_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(negedge C) begin
+ if (E) Q <= D;
+end
+endmodule
+
+module \$_DFFE_PN_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(posedge C) begin
+ if (!E) Q <= D;
+end
+endmodule
+
+module \$_DFFE_PP_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(posedge C) begin
+ if (E) Q <= D;
+end
+endmodule
+
module \$_DFF_NN0_ (D, Q, C, R);
input D, C, R;
output reg Q;
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 2d8088adb..abd2af521 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1160,12 +1160,51 @@ module \$assert (A, EN);
input A, EN;
+`ifndef SIMLIB_NOCHECKS
always @* begin
if (A !== 1'b1 && EN === 1'b1) begin
- $display("Assertation failed!");
- $finish;
+ $display("Assertation %m failed!");
+ $stop;
+ end
+end
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$assume (A, EN);
+
+input A, EN;
+
+`ifndef SIMLIB_NOCHECKS
+always @* begin
+ if (A !== 1'b1 && EN === 1'b1) begin
+ $display("Assumption %m failed!");
+ $stop;
+ end
+end
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$equiv (A, B, Y);
+
+input A, B;
+output Y;
+
+assign Y = (A !== 1'bx && A !== B) ? 1'bx : A;
+
+`ifndef SIMLIB_NOCHECKS
+always @* begin
+ if (A !== 1'bx && A !== B) begin
+ $display("Equivalence failed!");
+ $stop;
end
end
+`endif
endmodule
@@ -1217,6 +1256,25 @@ end
endmodule
// --------------------------------------------------------
+
+module \$dffe (CLK, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+
+input CLK, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+
+always @(posedge pos_clk) begin
+ if (EN == EN_POLARITY) Q <= D;
+end
+
+endmodule
+
+// --------------------------------------------------------
`ifndef SIMLIB_NOSR
module \$dffsr (CLK, SET, CLR, D, Q);
@@ -1287,7 +1345,7 @@ output reg [WIDTH-1:0] Q;
always @* begin
if (EN == EN_POLARITY)
- Q <= D;
+ Q = D;
end
endmodule
@@ -1315,11 +1373,11 @@ generate
for (i = 0; i < WIDTH; i = i+1) begin:bit
always @*
if (pos_clr[i])
- Q[i] <= 0;
+ Q[i] = 0;
else if (pos_set[i])
- Q[i] <= 1;
+ Q[i] = 1;
else if (pos_en)
- Q[i] <= D[i];
+ Q[i] = D[i];
end
endgenerate
@@ -1430,6 +1488,7 @@ parameter WIDTH = 8;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
+parameter TRANSPARENT = 0;
input CLK;
input [ABITS-1:0] ADDR;
@@ -1454,6 +1513,7 @@ parameter WIDTH = 8;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
+parameter PRIORITY = 0;
input CLK;
input [WIDTH-1:0] EN;
@@ -1471,13 +1531,36 @@ endmodule
// --------------------------------------------------------
+module \$meminit (ADDR, DATA);
+
+parameter MEMID = "";
+parameter ABITS = 8;
+parameter WIDTH = 8;
+
+parameter PRIORITY = 0;
+
+input [ABITS-1:0] ADDR;
+input [WIDTH-1:0] DATA;
+
+initial begin
+ if (MEMID != "") begin
+ $display("ERROR: Found non-simulatable instance of $meminit!");
+ $finish;
+ end
+end
+
+endmodule
+
+// --------------------------------------------------------
+
module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
parameter MEMID = "";
-parameter SIZE = 256;
+parameter SIZE = 4;
parameter OFFSET = 0;
-parameter ABITS = 8;
+parameter ABITS = 2;
parameter WIDTH = 8;
+parameter signed INIT = 1'bx;
parameter RD_PORTS = 1;
parameter RD_CLK_ENABLE = 1'b1;
@@ -1497,107 +1580,62 @@ input [WR_PORTS*WIDTH-1:0] WR_EN;
input [WR_PORTS*ABITS-1:0] WR_ADDR;
input [WR_PORTS*WIDTH-1:0] WR_DATA;
-reg [WIDTH-1:0] data [SIZE-1:0];
-reg update_async_rd;
+reg [WIDTH-1:0] memory [SIZE-1:0];
-genvar i;
-generate
+integer i, j;
+reg [WR_PORTS-1:0] LAST_WR_CLK;
+reg [RD_PORTS-1:0] LAST_RD_CLK;
+
+function port_active;
+ input clk_enable;
+ input clk_polarity;
+ input last_clk;
+ input this_clk;
+ begin
+ casez ({clk_enable, clk_polarity, last_clk, this_clk})
+ 4'b0???: port_active = 1;
+ 4'b1101: port_active = 1;
+ 4'b1010: port_active = 1;
+ default: port_active = 0;
+ endcase
+ end
+endfunction
- for (i = 0; i < RD_PORTS; i = i+1) begin:rd
- if (RD_CLK_ENABLE[i] == 0) begin:rd_noclk
- always @(RD_ADDR or update_async_rd)
- RD_DATA[i*WIDTH +: WIDTH] <= data[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
- end else
- if (RD_TRANSPARENT[i] == 1) begin:rd_transparent
- reg [ABITS-1:0] addr_buf;
- if (RD_CLK_POLARITY[i] == 1) begin:rd_trans_posclk
- always @(posedge RD_CLK[i])
- addr_buf <= RD_ADDR[i*ABITS +: ABITS];
- end else begin:rd_trans_negclk
- always @(negedge RD_CLK[i])
- addr_buf <= RD_ADDR[i*ABITS +: ABITS];
- end
- always @(addr_buf or update_async_rd)
- RD_DATA[i*WIDTH +: WIDTH] <= data[addr_buf - OFFSET];
- end else begin:rd_notransparent
- if (RD_CLK_POLARITY[i] == 1) begin:rd_notrans_posclk
- always @(posedge RD_CLK[i])
- RD_DATA[i*WIDTH +: WIDTH] <= data[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
- end else begin:rd_notrans_negclk
- always @(negedge RD_CLK[i])
- RD_DATA[i*WIDTH +: WIDTH] <= data[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
- end
+initial begin
+ for (i = 0; i < SIZE; i = i+1)
+ memory[i] = INIT >>> (i*WIDTH);
+end
+
+always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
+`ifdef SIMLIB_MEMDELAY
+ #`SIMLIB_MEMDELAY;
+`endif
+ for (i = 0; i < RD_PORTS; i = i+1) begin
+ if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
+ // $display("Read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
+ RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
end
end
- for (i = 0; i < WR_PORTS; i = i+1) begin:wr
- integer k, n;
- reg found_collision, run_update;
- if (WR_CLK_ENABLE[i] == 0) begin:wr_noclk
- always @(WR_ADDR or WR_DATA or WR_EN) begin
- run_update = 0;
- for (n = 0; n < WIDTH; n = n+1) begin
- if (WR_EN[i*WIDTH + n]) begin
- found_collision = 0;
- for (k = i+1; k < WR_PORTS; k = k+1)
- if (WR_EN[k*WIDTH + n] && WR_ADDR[i*ABITS +: ABITS] == WR_ADDR[k*ABITS +: ABITS])
- found_collision = 1;
- if (!found_collision) begin
- data[WR_ADDR[i*ABITS +: ABITS] - OFFSET][n] <= WR_DATA[i*WIDTH + n];
- run_update = 1;
- end
- end
- end
- if (run_update) begin
- update_async_rd <= 1;
- update_async_rd <= 0;
+ for (i = 0; i < WR_PORTS; i = i+1) begin
+ if (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))
+ for (j = 0; j < WIDTH; j = j+1)
+ if (WR_EN[i*WIDTH+j]) begin
+ // $display("Write to %s: addr=%b data=%b", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);
+ memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
end
- end
- end else
- if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk
- always @(posedge WR_CLK[i]) begin
- run_update = 0;
- for (n = 0; n < WIDTH; n = n+1) begin
- if (WR_EN[i*WIDTH + n]) begin
- found_collision = 0;
- for (k = i+1; k < WR_PORTS; k = k+1)
- if (WR_EN[k*WIDTH + n] && WR_ADDR[i*ABITS +: ABITS] == WR_ADDR[k*ABITS +: ABITS])
- found_collision = 1;
- if (!found_collision) begin
- data[WR_ADDR[i*ABITS +: ABITS] - OFFSET][n] <= WR_DATA[i*WIDTH + n];
- run_update = 1;
- end
- end
- end
- if (run_update) begin
- update_async_rd <= 1;
- update_async_rd <= 0;
- end
- end
- end else begin:rd_negclk
- always @(negedge WR_CLK[i]) begin
- run_update = 0;
- for (n = 0; n < WIDTH; n = n+1) begin
- if (WR_EN[i*WIDTH + n]) begin
- found_collision = 0;
- for (k = i+1; k < WR_PORTS; k = k+1)
- if (WR_EN[k*WIDTH + n] && WR_ADDR[i*ABITS +: ABITS] == WR_ADDR[k*ABITS +: ABITS])
- found_collision = 1;
- if (!found_collision) begin
- data[WR_ADDR[i*ABITS +: ABITS] - OFFSET][n] <= WR_DATA[i*WIDTH + n];
- run_update = 1;
- end
- end
- end
- if (run_update) begin
- update_async_rd <= 1;
- update_async_rd <= 0;
- end
- end
+ end
+
+ for (i = 0; i < RD_PORTS; i = i+1) begin
+ if ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
+ // $display("Transparent read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
+ RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
end
end
-endgenerate
+ LAST_RD_CLK <= RD_CLK;
+ LAST_WR_CLK <= WR_CLK;
+end
endmodule
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 4ccacd30b..c3e7288db 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -22,7 +22,10 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
-static bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
{
if (!run_from.empty() && run_from == run_to) {
active = (label == run_from);
@@ -49,6 +52,12 @@ struct SynthPass : public Pass {
log(" -top <module>\n");
log(" use the specified module as top module (default='top')\n");
log("\n");
+ log(" -encfile <file>\n");
+ log(" passed to 'fsm_recode' via 'fsm'\n");
+ log("\n");
+ log(" -noabc\n");
+ log(" do not run abc (as if yosys was compiled without ABC support)\n");
+ log("\n");
log(" -run <from_label>[:<to_label>]\n");
log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
@@ -62,6 +71,8 @@ struct SynthPass : public Pass {
log("\n");
log(" coarse:\n");
log(" proc\n");
+ log(" opt_clean\n");
+ log(" check\n");
log(" opt\n");
log(" wreduce\n");
log(" alumacc\n");
@@ -73,19 +84,27 @@ struct SynthPass : public Pass {
log(" opt_clean\n");
log("\n");
log(" fine:\n");
+ log(" opt -fast -full\n");
log(" memory_map\n");
+ log(" opt -full\n");
log(" techmap\n");
log(" opt -fast\n");
#ifdef YOSYS_ENABLE_ABC
log(" abc -fast\n");
- log(" opt_clean\n");
+ log(" opt -fast\n");
#endif
log("\n");
+ log(" check:\n");
+ log(" hierarchy -check\n");
+ log(" stat\n");
+ log(" check\n");
+ log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
- std::string top_module;
+ std::string top_module, fsm_opts;
std::string run_from, run_to;
+ bool noabc = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -94,6 +113,10 @@ struct SynthPass : public Pass {
top_module = args[++argidx];
continue;
}
+ if (args[argidx] == "-encfile" && argidx+1 < args.size()) {
+ fsm_opts = " -encfile " + args[++argidx];
+ continue;
+ }
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos) {
@@ -105,6 +128,10 @@ struct SynthPass : public Pass {
}
continue;
}
+ if (args[argidx] == "-noabc") {
+ noabc = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -128,12 +155,14 @@ struct SynthPass : public Pass {
if (check_label(active, run_from, run_to, "coarse"))
{
Pass::call(design, "proc");
+ Pass::call(design, "opt_clean");
+ Pass::call(design, "check");
Pass::call(design, "opt");
Pass::call(design, "wreduce");
Pass::call(design, "alumacc");
Pass::call(design, "share");
Pass::call(design, "opt");
- Pass::call(design, "fsm");
+ Pass::call(design, "fsm" + fsm_opts);
Pass::call(design, "opt -fast");
Pass::call(design, "memory -nomap");
Pass::call(design, "opt_clean");
@@ -141,16 +170,29 @@ struct SynthPass : public Pass {
if (check_label(active, run_from, run_to, "fine"))
{
+ Pass::call(design, "opt -fast -full");
Pass::call(design, "memory_map");
+ Pass::call(design, "opt -full");
Pass::call(design, "techmap");
Pass::call(design, "opt -fast");
+
+ if (!noabc) {
#ifdef YOSYS_ENABLE_ABC
- Pass::call(design, "abc -fast");
- Pass::call(design, "opt_clean");
+ Pass::call(design, "abc -fast");
+ Pass::call(design, "opt -fast");
#endif
+ }
+ }
+
+ if (check_label(active, run_from, run_to, "check"))
+ {
+ Pass::call(design, "hierarchy -check");
+ Pass::call(design, "stat");
+ Pass::call(design, "check");
}
log_pop();
}
} SynthPass;
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index b6c075b67..e0ecf0c48 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -54,12 +54,17 @@ module _90_simplemap_logic_ops;
endmodule
(* techmap_simplemap *)
+(* techmap_celltype = "$eq $eqx $ne $nex" *)
+module _90_simplemap_compare_ops;
+endmodule
+
+(* techmap_simplemap *)
(* techmap_celltype = "$pos $slice $concat $mux" *)
module _90_simplemap_various;
endmodule
(* techmap_simplemap *)
-(* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
+(* techmap_celltype = "$sr $dff $dffe $adff $dffsr $dlatch" *)
module _90_simplemap_registers;
endmodule
@@ -207,7 +212,7 @@ module _90_lcu (P, G, CI, CO);
g[0] = g[0] | (p[0] & CI);
// [[CITE]] Brent Kung Adder
- // R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders”,
+ // R. P. Brent and H. T. Kung, "A Regular Layout for Parallel Adders",
// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
// Main tree
@@ -407,55 +412,6 @@ endmodule
// --------------------------------------------------------
-// Equal and Not-Equal
-// --------------------------------------------------------
-
-(* techmap_celltype = "$eq $eqx" *)
-module _90_eq_eqx (A, B, Y);
- parameter A_SIGNED = 0;
- parameter B_SIGNED = 0;
- parameter A_WIDTH = 1;
- parameter B_WIDTH = 1;
- parameter Y_WIDTH = 1;
-
- localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
-
- input [A_WIDTH-1:0] A;
- input [B_WIDTH-1:0] B;
- output [Y_WIDTH-1:0] Y;
-
- wire carry, carry_sign;
- wire [WIDTH-1:0] A_buf, B_buf;
- \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
- \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
-
- assign Y = ~|(A_buf ^ B_buf);
-endmodule
-
-(* techmap_celltype = "$ne $nex" *)
-module _90_ne_nex (A, B, Y);
- parameter A_SIGNED = 0;
- parameter B_SIGNED = 0;
- parameter A_WIDTH = 1;
- parameter B_WIDTH = 1;
- parameter Y_WIDTH = 1;
-
- localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
-
- input [A_WIDTH-1:0] A;
- input [B_WIDTH-1:0] B;
- output [Y_WIDTH-1:0] Y;
-
- wire carry, carry_sign;
- wire [WIDTH-1:0] A_buf, B_buf;
- \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
- \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
-
- assign Y = |(A_buf ^ B_buf);
-endmodule
-
-
-// --------------------------------------------------------
// Parallel Multiplexers
// --------------------------------------------------------
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