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-rw-r--r--techlibs/common/abc9_map.v2
-rw-r--r--techlibs/common/gen_fine_ffs.py153
-rw-r--r--techlibs/common/prep.cc12
-rw-r--r--techlibs/common/simcells.v1984
-rw-r--r--techlibs/common/simlib.v172
-rw-r--r--techlibs/common/synth.cc14
-rw-r--r--techlibs/common/techmap.v104
7 files changed, 2356 insertions, 85 deletions
diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v
index 6ed90b5f5..b00e0e6a8 100644
--- a/techlibs/common/abc9_map.v
+++ b/techlibs/common/abc9_map.v
@@ -1,5 +1,5 @@
`ifdef DFF
-(* techmap_celltype = "$_DFF_N_ $_DFF_P_" *)
+(* techmap_celltype = "$_DFF_[PN]_" *)
module $_DFF_x_(input C, D, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
parameter _TECHMAP_CELLTYPE_ = "";
diff --git a/techlibs/common/gen_fine_ffs.py b/techlibs/common/gen_fine_ffs.py
index 0abe48f61..5d331e767 100644
--- a/techlibs/common/gen_fine_ffs.py
+++ b/techlibs/common/gen_fine_ffs.py
@@ -108,6 +108,31 @@ endmodule
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
+//- $_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity {V:reset|set} and {E:negative|positive}
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - {R:0|1} - | {V:0|1}
+//- d {C:\\|/} - {E:0|1} | d
+//- - - - - | q
+//-
+module \$_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @({C:neg|pos}edge C or {R:neg|pos}edge R) begin
+ if (R == {R:0|1})
+ Q <= {V:0|1};
+ else if (E == {E:0|1})
+ Q <= D;
+end
+endmodule
+""",
+"""
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
//- $_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q)
//-
//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set and {R:negative|positive}
@@ -136,6 +161,110 @@ endmodule
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
+//- $_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set, {R:negative|positive}
+//- polarity reset and {E:negative|positive} polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - {R:0|1} - - | 0
+//- - {S:0|1} - - - | 1
+//- {C:\\|/} - - {E:0|1} d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @({C:neg|pos}edge C, {S:neg|pos}edge S, {R:neg|pos}edge R) begin
+ if (R == {R:0|1})
+ Q <= 0;
+ else if (S == {S:0|1})
+ Q <= 1;
+ else if (E == {E:0|1})
+ Q <= D;
+end
+endmodule
+""",
+"""
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set}.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - {C:\\|/} {R:0|1} | {V:0|1}
+//- d {C:\\|/} - | d
+//- - - - | q
+//-
+module \$_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @({C:neg|pos}edge C) begin
+ if (R == {R:0|1})
+ Q <= {V:0|1};
+ else
+ Q <= D;
+end
+endmodule
+""",
+"""
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set} and {E:negative|positive}
+//- polarity clock enable (with {V:reset|set} having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - {C:\\|/} {R:0|1} - | {V:0|1}
+//- d {C:\\|/} - {E:0|1} | d
+//- - - - - | q
+//-
+module \$_SDFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @({C:neg|pos}edge C) begin
+ if (R == {R:0|1})
+ Q <= {V:0|1};
+ else if (E == {E:0|1})
+ Q <= D;
+end
+endmodule
+""",
+"""
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set} and {E:negative|positive}
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - {C:\\|/} {R:0|1} {E:0|1} | {V:0|1}
+//- d {C:\\|/} - {E:0|1} | d
+//- - - - - | q
+//-
+module \$_SDFFCE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @({C:neg|pos}edge C) begin
+ if (E == {E:0|1}) begin
+ if (R == {R:0|1})
+ Q <= {V:0|1};
+ else
+ Q <= D;
+ end
+end
+endmodule
+""",
+"""
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
//- $_DLATCH_{E:N|P}_ (E, D, Q)
//-
//- A {E:negative|positive} enable D-type latch.
@@ -157,6 +286,30 @@ endmodule
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
+//- $_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q)
+//-
+//- A {E:negative|positive} enable D-type latch with {R:negative|positive} polarity {V:reset|set}.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - {R:0|1} - | {V:0|1}
+//- {E:0|1} - d | d
+//- - - - | q
+//-
+module \$_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == {R:0|1})
+ Q <= {V:0|1};
+ else if (E == {E:0|1})
+ Q <= D;
+end
+endmodule
+""",
+"""
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
//- $_DLATCHSR_{E:N|P}{S:N|P}{R:N|P}_ (E, S, R, D, Q)
//-
//- A {E:negative|positive} enable D-type latch with {S:negative|positive} polarity set and {R:negative|positive}
diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc
index cdd21c3b3..93b0910d6 100644
--- a/techlibs/common/prep.cc
+++ b/techlibs/common/prep.cc
@@ -29,7 +29,7 @@ struct PrepPass : public ScriptPass
{
PrepPass() : ScriptPass("prep", "generic synthesis script") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -81,7 +81,7 @@ struct PrepPass : public ScriptPass
string top_module, fsm_opts;
bool autotop, flatten, ifxmode, memxmode, nomemmode, nokeepdc, nordff;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_module.clear();
@@ -94,7 +94,7 @@ struct PrepPass : public ScriptPass
nordff = true;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
@@ -163,7 +163,7 @@ struct PrepPass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
@@ -192,7 +192,7 @@ struct PrepPass : public ScriptPass
run(nokeepdc ? "opt_expr" : "opt_expr -keepdc");
run("opt_clean");
run("check");
- run(nokeepdc ? "opt" : "opt -keepdc");
+ run(nokeepdc ? "opt -noff" : "opt -noff -keepdc");
if (!ifxmode) {
if (help_mode)
run("wreduce -keepdc [-memx]");
@@ -208,7 +208,7 @@ struct PrepPass : public ScriptPass
run("opt_clean");
run("memory_collect");
}
- run(nokeepdc ? "opt -fast" : "opt -keepdc -fast");
+ run(nokeepdc ? "opt -noff -fast" : "opt -noff -keepdc -fast");
}
if (check_label("check"))
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 157e8d23b..27ef44232 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -870,6 +870,390 @@ endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
+//- $_DFFE_NN0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 0
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_NN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NN0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 0
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_NN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NN1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 1
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_NN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NN1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 1
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_NN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NP0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 0
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_NP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NP0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 0
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_NP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NP1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 1
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_NP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NP1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 1
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_NP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PN0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 0
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_PN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PN0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 0
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_PN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PN1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 1
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_PN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PN1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 1
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_PN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PP0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 0
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_PP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PP0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 0
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_PP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PP1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 1
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_PP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PP1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 1
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_PP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
//- $_DFFSR_NNN_ (C, S, R, D, Q)
//-
//- A negative edge D-type flip-flop with negative polarity set and negative
@@ -1086,6 +1470,1422 @@ endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
+//- $_DFFSRE_NNNN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 0 - - - | 1
+//- \ - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NNNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NNNP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 0 - - - | 1
+//- \ - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NNPN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 0 - - - | 1
+//- \ - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NNPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NNPP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 0 - - - | 1
+//- \ - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NNPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NPNN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 1 - - - | 1
+//- \ - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NPNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NPNP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 1 - - - | 1
+//- \ - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NPNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NPPN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 1 - - - | 1
+//- \ - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NPPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NPPP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 1 - - - | 1
+//- \ - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NPPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PNNN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 0 - - - | 1
+//- / - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PNNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PNNP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 0 - - - | 1
+//- / - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PNPN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 0 - - - | 1
+//- / - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PNPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PNPP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 0 - - - | 1
+//- / - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PNPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PPNN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 1 - - - | 1
+//- / - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PPNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PPNP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 1 - - - | 1
+//- / - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PPNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PPPN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 1 - - - | 1
+//- / - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PPPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PPPP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 1 - - - | 1
+//- / - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PPPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_NN0_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - \ 0 | 0
+//- d \ - | d
+//- - - - | q
+//-
+module \$_SDFF_NN0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_NN1_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - \ 0 | 1
+//- d \ - | d
+//- - - - | q
+//-
+module \$_SDFF_NN1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_NP0_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - \ 1 | 0
+//- d \ - | d
+//- - - - | q
+//-
+module \$_SDFF_NP0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_NP1_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - \ 1 | 1
+//- d \ - | d
+//- - - - | q
+//-
+module \$_SDFF_NP1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_PN0_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - / 0 | 0
+//- d / - | d
+//- - - - | q
+//-
+module \$_SDFF_PN0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_PN1_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - / 0 | 1
+//- d / - | d
+//- - - - | q
+//-
+module \$_SDFF_PN1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_PP0_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - / 1 | 0
+//- d / - | d
+//- - - - | q
+//-
+module \$_SDFF_PP0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_PP1_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - / 1 | 1
+//- d / - | d
+//- - - - | q
+//-
+module \$_SDFF_PP1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NN0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 - | 0
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NN0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 - | 0
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NN1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 - | 1
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NN1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 - | 1
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NP0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 - | 0
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NP0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 - | 0
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NP1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 - | 1
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NP1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 - | 1
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PN0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 - | 0
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PN0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 - | 0
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PN1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 - | 1
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PN1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 - | 1
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PP0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 - | 0
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PP0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 - | 0
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PP1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 - | 1
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PP1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 - | 1
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NN0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 0 | 0
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 0) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NN0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 1 | 0
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 1) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NN1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 0 | 1
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 0) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NN1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 1 | 1
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 1) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NP0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 0 | 0
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 0) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NP0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 1 | 0
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 1) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NP1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 0 | 1
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 0) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NP1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 1 | 1
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 1) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PN0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 0 | 0
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 0) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PN0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 1 | 0
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 1) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PN1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 0 | 1
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 0) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PN1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 1 | 1
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 1) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PP0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 0 | 0
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 0) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PP0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 1 | 0
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 1) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PP1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 0 | 1
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 0) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PP1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 1 | 1
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 1) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
//- $_DLATCH_N_ (E, D, Q)
//-
//- A negative enable D-type latch.
@@ -1126,6 +2926,190 @@ endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
+//- $_DLATCH_NN0_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with negative polarity reset.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 0 - | 0
+//- 0 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_NN0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_NN1_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with negative polarity set.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 0 - | 1
+//- 0 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_NN1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_NP0_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with positive polarity reset.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 1 - | 0
+//- 0 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_NP0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_NP1_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with positive polarity set.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 1 - | 1
+//- 0 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_NP1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_PN0_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with negative polarity reset.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 0 - | 0
+//- 1 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_PN0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_PN1_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with negative polarity set.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 0 - | 1
+//- 1 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_PN1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_PP0_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with positive polarity reset.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 1 - | 0
+//- 1 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_PP0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_PP1_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with positive polarity set.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 1 - | 1
+//- 1 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_PP1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
//- $_DLATCHSR_NNN_ (E, S, R, D, Q)
//-
//- A negative enable D-type latch with negative polarity set and negative
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 125b8e013..e94884025 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -480,10 +480,18 @@ input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
- if (B_SIGNED) begin:BLOCK1
- assign Y = $signed(B) < 0 ? A << -B : A >> B;
- end else begin:BLOCK2
- assign Y = A >> B;
+ if (A_SIGNED) begin:BLOCK1
+ if (B_SIGNED) begin:BLOCK2
+ assign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;
+ end else begin:BLOCK3
+ assign Y = $signed(A) >> B;
+ end
+ end else begin:BLOCK4
+ if (B_SIGNED) begin:BLOCK5
+ assign Y = $signed(B) < 0 ? A << -B : A >> B;
+ end else begin:BLOCK6
+ assign Y = A >> B;
+ end
end
endgenerate
@@ -1822,6 +1830,39 @@ endgenerate
endmodule
+// --------------------------------------------------------
+
+module \$dffsre (CLK, SET, CLR, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter SET_POLARITY = 1'b1;
+parameter CLR_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+
+input CLK, EN;
+input [WIDTH-1:0] SET, CLR, D;
+output reg [WIDTH-1:0] Q;
+
+wire pos_clk = CLK == CLK_POLARITY;
+wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
+wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
+
+genvar i;
+generate
+ for (i = 0; i < WIDTH; i = i+1) begin:bitslices
+ always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
+ if (pos_clr[i])
+ Q[i] <= 0;
+ else if (pos_set[i])
+ Q[i] <= 1;
+ else if (EN == EN_POLARITY)
+ Q[i] <= D[i];
+ end
+endgenerate
+
+endmodule
+
`endif
// --------------------------------------------------------
@@ -1849,6 +1890,107 @@ endmodule
// --------------------------------------------------------
+module \$sdff (CLK, SRST, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter SRST_POLARITY = 1'b1;
+parameter SRST_VALUE = 0;
+
+input CLK, SRST;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_srst = SRST == SRST_POLARITY;
+
+always @(posedge pos_clk) begin
+ if (pos_srst)
+ Q <= SRST_VALUE;
+ else
+ Q <= D;
+end
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$adffe (CLK, ARST, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+parameter ARST_POLARITY = 1'b1;
+parameter ARST_VALUE = 0;
+
+input CLK, ARST, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_arst = ARST == ARST_POLARITY;
+
+always @(posedge pos_clk, posedge pos_arst) begin
+ if (pos_arst)
+ Q <= ARST_VALUE;
+ else if (EN == EN_POLARITY)
+ Q <= D;
+end
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$sdffe (CLK, SRST, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+parameter SRST_POLARITY = 1'b1;
+parameter SRST_VALUE = 0;
+
+input CLK, SRST, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_srst = SRST == SRST_POLARITY;
+
+always @(posedge pos_clk) begin
+ if (pos_srst)
+ Q <= SRST_VALUE;
+ else if (EN == EN_POLARITY)
+ Q <= D;
+end
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$sdffce (CLK, SRST, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+parameter SRST_POLARITY = 1'b1;
+parameter SRST_VALUE = 0;
+
+input CLK, SRST, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_srst = SRST == SRST_POLARITY;
+
+always @(posedge pos_clk) begin
+ if (EN == EN_POLARITY) begin
+ if (pos_srst)
+ Q <= SRST_VALUE;
+ else
+ Q <= D;
+ end
+end
+
+endmodule
+
+// --------------------------------------------------------
+
module \$dlatch (EN, D, Q);
parameter WIDTH = 0;
@@ -1866,6 +2008,28 @@ end
endmodule
// --------------------------------------------------------
+
+module \$adlatch (EN, ARST, D, Q);
+
+parameter WIDTH = 0;
+parameter EN_POLARITY = 1'b1;
+parameter ARST_POLARITY = 1'b1;
+parameter ARST_VALUE = 0;
+
+input EN, ARST;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+
+always @* begin
+ if (ARST == ARST_POLARITY)
+ Q = ARST_VALUE;
+ else if (EN == EN_POLARITY)
+ Q = D;
+end
+
+endmodule
+
+// --------------------------------------------------------
`ifndef SIMLIB_NOSR
module \$dlatchsr (EN, SET, CLR, D, Q);
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index d6dffdd7f..89d6e530e 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -29,7 +29,7 @@ struct SynthPass : public ScriptPass
{
SynthPass() : ScriptPass("synth", "generic synthesis script") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -91,7 +91,7 @@ struct SynthPass : public ScriptPass
bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap;
int lut;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_module.clear();
fsm_opts.clear();
@@ -108,7 +108,7 @@ struct SynthPass : public ScriptPass
abc = "abc";
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -195,7 +195,7 @@ struct SynthPass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
{
@@ -220,6 +220,9 @@ struct SynthPass : public ScriptPass
run("opt_expr");
run("opt_clean");
run("check");
+ run("opt -nodffe -nosdff");
+ if (!nofsm)
+ run("fsm" + fsm_opts, " (unless -nofsm)");
run("opt");
run("wreduce");
run("peepopt");
@@ -233,9 +236,6 @@ struct SynthPass : public ScriptPass
if (!noshare)
run("share", " (unless -noshare)");
run("opt");
- if (!nofsm)
- run("fsm" + fsm_opts, " (unless -nofsm)");
- run("opt -fast");
run("memory -nomap" + memory_opts);
run("opt_clean");
}
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index eafe8d4da..2ab28e6e6 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -64,7 +64,7 @@ module _90_simplemap_various;
endmodule
(* techmap_simplemap *)
-(* techmap_celltype = "$sr $ff $dff $dffe $adff $dffsr $dlatch" *)
+(* techmap_celltype = "$sr $ff $dff $dffe $adff $adffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr" *)
module _90_simplemap_registers;
endmodule
@@ -141,78 +141,48 @@ module _90_shift_shiftx (A, B, Y);
parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
+ wire a_padding = _TECHMAP_CELLTYPE_ == "$shiftx" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);
- generate
-`ifndef NO_LSB_FIRST_SHIFT_SHIFTX
- // If $shift/$shiftx only shifts in units of Y_WIDTH
- // (a common pattern created by pmux2shiftx)
- // which is checked by ensuring that all that
- // the appropriate LSBs of B are constant zero,
- // then we can decompose LSB first instead of
- // MSB first
- localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH);
- if (B_WIDTH > CLOG2_Y_WIDTH+1 &&
- _TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} &&
- _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin
- // Halve the size of $shift/$shiftx by $mux-ing A according to
- // the LSB of B, after discarding the zeroed bits
- localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
- localparam entries = (A_WIDTH+Y_WIDTH-1)/Y_WIDTH2;
- localparam len = Y_WIDTH2 * ((entries+1)/2);
- wire [len-1:0] AA;
- wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){extbit}}, A};
- genvar i;
- for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2)
- assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? Apad[i+Y_WIDTH2 +: Y_WIDTH2] : Apad[i +: Y_WIDTH2];
- wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
- if (_TECHMAP_CELLTYPE_ == "$shift")
- $shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
- else
- $shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
- end
- else
-`endif
- begin
- localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
- localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
+ localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
+ localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
- wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
- wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
+ wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
+ wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
- integer i;
- (* force_downto *)
- reg [WIDTH-1:0] buffer;
- reg overflow;
+ integer i;
+ (* force_downto *)
+ reg [WIDTH-1:0] buffer;
+ reg overflow;
- always @* begin
- overflow = 0;
+ always @* begin
+ overflow = 0;
+ buffer = {WIDTH{extbit}};
+ buffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};
+ buffer[A_WIDTH-1:0] = A;
+
+ if (B_WIDTH > BB_WIDTH) begin
+ if (B_SIGNED) begin
+ for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
+ if (B[i] != B[BB_WIDTH-1])
+ overflow = 1;
+ end else
+ overflow = |B[B_WIDTH-1:BB_WIDTH];
+ if (overflow)
buffer = {WIDTH{extbit}};
- buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
-
- if (B_WIDTH > BB_WIDTH) begin
- if (B_SIGNED) begin
- for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
- if (B[i] != B[BB_WIDTH-1])
- overflow = 1;
- end else
- overflow = |B[B_WIDTH-1:BB_WIDTH];
- if (overflow)
- buffer = {WIDTH{extbit}};
- end
-
- for (i = BB_WIDTH-1; i >= 0; i = i-1)
- if (B[i]) begin
- if (B_SIGNED && i == BB_WIDTH-1)
- buffer = {buffer, {2**i{extbit}}};
- else if (2**i < WIDTH)
- buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
- else
- buffer = {WIDTH{extbit}};
- end
- end
- assign Y = buffer;
end
- endgenerate
+
+ if (B_SIGNED && B[BB_WIDTH-1])
+ buffer = {buffer, {2**(BB_WIDTH-1){extbit}}};
+
+ for (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)
+ if (B[i]) begin
+ if (2**i < WIDTH)
+ buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
+ else
+ buffer = {WIDTH{extbit}};
+ end
+ end
+ assign Y = buffer;
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-12 23:54:03 +0000