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-rw-r--r--techlibs/common/simlib.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index d0feadd81..a73c6ee09 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1328,7 +1328,7 @@ output reg [WIDTH-1:0] Q;
always @* begin
if (EN == EN_POLARITY)
- Q <= D;
+ Q = D;
end
endmodule
@@ -1356,11 +1356,11 @@ generate
for (i = 0; i < WIDTH; i = i+1) begin:bit
always @*
if (pos_clr[i])
- Q[i] <= 0;
+ Q[i] = 0;
else if (pos_set[i])
- Q[i] <= 1;
+ Q[i] = 1;
else if (pos_en)
- Q[i] <= D[i];
+ Q[i] = D[i];
end
endgenerate