2 files changed, 20 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 2d8088adb..e241cd3ce 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1217,6 +1217,25 @@ end
 endmodule
 
 // --------------------------------------------------------
+
+module \$dffe (CLK, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+
+input CLK, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+
+always @(posedge pos_clk) begin
+	if (EN == EN_POLARITY) Q <= D;
+end
+
+endmodule
+
+// --------------------------------------------------------
 `ifndef SIMLIB_NOSR
 
 module \$dffsr (CLK, SET, CLR, D, Q);
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index b6c075b67..cb39fb4b2 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -59,7 +59,7 @@ module _90_simplemap_various;
 endmodule
 
 (* techmap_simplemap *)
-(* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
+(* techmap_celltype = "$sr $dff $dffe $adff $dffsr $dlatch" *)
 module _90_simplemap_registers;
 endmodule