aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/ecp5
diff options
context:
space:
mode:
Diffstat (limited to 'techlibs/ecp5')
-rw-r--r--techlibs/ecp5/Makefile.inc3
-rw-r--r--techlibs/ecp5/abc9_5g.box36
-rw-r--r--techlibs/ecp5/abc9_5g.lut25
-rw-r--r--techlibs/ecp5/abc9_5g_nowide.lut12
-rw-r--r--techlibs/ecp5/abc9_model.v9
-rw-r--r--techlibs/ecp5/brams_map.v2
-rw-r--r--techlibs/ecp5/cells_sim.v95
-rw-r--r--techlibs/ecp5/ecp5_ffinit.cc44
-rw-r--r--techlibs/ecp5/ecp5_gsr.cc4
-rw-r--r--techlibs/ecp5/synth_ecp5.cc8
10 files changed, 126 insertions, 112 deletions
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 2c33f23b9..e4ee4991f 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -18,9 +18,6 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.box))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.lut))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g_nowide.lut))
EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
.SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
diff --git a/techlibs/ecp5/abc9_5g.box b/techlibs/ecp5/abc9_5g.box
deleted file mode 100644
index f153a665e..000000000
--- a/techlibs/ecp5/abc9_5g.box
+++ /dev/null
@@ -1,36 +0,0 @@
-# NB: Box inputs/outputs must each be in the same order
-# as their corresponding module definition
-# (with exceptions detailed below)
-
-# Box 1 : CCU2C (2xCARRY + 2xLUT4)
-# (Exception: carry chain input/output must be the
-# last input and output and the entire bus has been
-# moved there overriding the otherwise
-# alphabetical ordering)
-# name ID w/b ins outs
-CCU2C 1 1 9 3
-#A0 B0 C0 D0 A1 B1 C1 D1 CIN
-379 379 275 141 - - - - 257 # S0
-630 630 526 392 379 379 275 141 273 # S1
-516 516 412 278 516 516 412 278 43 # COUT
-
-# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
-# name ID w/b ins outs
-$__ABC9_DPR16X4_COMB 2 0 8 4
-#$DO0 $DO1 $DO2 $DO3 RAD0 RAD1 RAD2 RAD3
-0 0 0 0 141 379 275 379 # DO0
-0 0 0 0 141 379 275 379 # DO1
-0 0 0 0 141 379 275 379 # DO2
-0 0 0 0 141 379 275 379 # DO3
-
-# Box 3 : PFUMX (MUX2)
-# name ID w/b ins outs
-PFUMX 3 1 3 1
-#ALUT BLUT C0
-98 98 151 # Z
-
-# Box 4 : L6MUX21 (MUX2)
-# name ID w/b ins outs
-L6MUX21 4 1 3 1
-#D0 D1 SD
-140 141 148 # Z
diff --git a/techlibs/ecp5/abc9_5g.lut b/techlibs/ecp5/abc9_5g.lut
deleted file mode 100644
index e8aa9b35d..000000000
--- a/techlibs/ecp5/abc9_5g.lut
+++ /dev/null
@@ -1,25 +0,0 @@
-# ECP5-5G LUT library for ABC
-# Note that ECP5 architecture assigns difference
-# in LUT input delay to interconnect, so this is
-# considered too
-
-
-# Simple LUTs
-# area D C B A
-1 1 141
-2 1 141 275
-3 1 141 275 379
-4 1 141 275 379 379
-
-# LUT5 = 2x LUT4 + PFUMX
-# area M0 D C B A
-5 2 151 239 373 477 477
-
-# LUT6 = 2x LUT5 + MUX2
-# area M1 M0 D C B A
-6 4 148 292 380 514 618 618
-
-# LUT7 = 2x LUT6 + MUX2
-# area M2 M1 M0 D C B A
-7 8 148 289 433 521 655 759 759
-
diff --git a/techlibs/ecp5/abc9_5g_nowide.lut b/techlibs/ecp5/abc9_5g_nowide.lut
deleted file mode 100644
index 60352d892..000000000
--- a/techlibs/ecp5/abc9_5g_nowide.lut
+++ /dev/null
@@ -1,12 +0,0 @@
-# ECP5-5G LUT library for ABC
-# Note that ECP5 architecture assigns difference
-# in LUT input delay to interconnect, so this is
-# considered too
-
-
-# Simple LUTs
-# area D C B A
-1 1 141
-2 1 141 275
-3 1 141 275 379
-4 1 141 275 379 379
diff --git a/techlibs/ecp5/abc9_model.v b/techlibs/ecp5/abc9_model.v
index 81e5cd070..b7ecd7358 100644
--- a/techlibs/ecp5/abc9_model.v
+++ b/techlibs/ecp5/abc9_model.v
@@ -1,5 +1,12 @@
// ---------------------------------------
-(* abc9_box_id=2 *)
+(* abc9_box *)
module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
+ specify
+ ($DO => DO) = 0;
+ (RAD[0] *> DO) = 141;
+ (RAD[1] *> DO) = 379;
+ (RAD[2] *> DO) = 275;
+ (RAD[3] *> DO) = 379;
+ endspecify
endmodule
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index 310aedaf2..edda17c02 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -137,8 +137,6 @@ module \$__ECP5_PDPW16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN
localparam CLKWMUX = CLKPOL2 ? "CLKA" : "INV";
localparam CLKRMUX = CLKPOL3 ? "CLKB" : "INV";
- localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
-
PDPW16KD #(
`include "bram_init_9_18_36.vh"
.DATA_WIDTH_W(36),
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 0d3ec4e5b..12b33e925 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -1,22 +1,78 @@
// ---------------------------------------
-(* lib_whitebox *)
+(* abc9_lut=1, lib_whitebox *)
module LUT4(input A, B, C, D, output Z);
parameter [15:0] INIT = 16'h0000;
wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
assign Z = A ? s1[1] : s1[0];
+ specify
+ (A => Z) = 141;
+ (B => Z) = 275;
+ (C => Z) = 379;
+ (D => Z) = 379;
+ endspecify
+endmodule
+
+// This is a placeholder for ABC9 to extract the area/delay
+// cost of 5-input LUTs and is not intended to be instantiated
+// LUT5 = 2x LUT4 + PFUMX
+(* abc9_lut=2 *)
+module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
+ specify
+ (M0 => Z) = 151;
+ (D => Z) = 239;
+ (C => Z) = 373;
+ (B => Z) = 477;
+ (A => Z) = 477;
+ endspecify
+endmodule
+
+// This is a placeholder for ABC9 to extract the area/delay
+// of 6-input LUTs and is not intended to be instantiated
+// LUT6 = 2x LUT5 + MUX2
+(* abc9_lut=4 *)
+module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
+ specify
+ (M1 => Z) = 148;
+ (M0 => Z) = 292;
+ (D => Z) = 380;
+ (C => Z) = 514;
+ (B => Z) = 618;
+ (A => Z) = 618;
+ endspecify
+endmodule
+
+// This is a placeholder for ABC9 to extract the area/delay
+// of 7-input LUTs and is not intended to be instantiated
+// LUT7 = 2x LUT6 + MUX2
+(* abc9_lut=8 *)
+module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);
+ specify
+ (M2 => Z) = 148;
+ (M1 => Z) = 289;
+ (M0 => Z) = 433;
+ (D => Z) = 521;
+ (C => Z) = 655;
+ (B => Z) = 759;
+ (A => Z) = 759;
+ endspecify
endmodule
// ---------------------------------------
-(* abc9_box_id=4, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
module L6MUX21 (input D0, D1, SD, output Z);
assign Z = SD ? D1 : D0;
+ specify
+ (D0 => Z) = 140;
+ (D1 => Z) = 141;
+ (SD => Z) = 148;
+ endspecify
endmodule
// ---------------------------------------
-(* abc9_box_id=1, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
module CCU2C(
(* abc9_carry *)
input CIN,
@@ -50,6 +106,31 @@ module CCU2C(
wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
+ specify
+ (A0 => S0) = 379;
+ (B0 => S0) = 379;
+ (C0 => S0) = 275;
+ (D0 => S0) = 141;
+ (CIN => S0) = 257;
+ (A0 => S1) = 630;
+ (B0 => S1) = 630;
+ (C0 => S1) = 526;
+ (D0 => S1) = 392;
+ (A1 => S1) = 379;
+ (B1 => S1) = 379;
+ (C1 => S1) = 275;
+ (D1 => S1) = 141;
+ (CIN => S1) = 273;
+ (A0 => COUT) = 516;
+ (B0 => COUT) = 516;
+ (C0 => COUT) = 412;
+ (D0 => COUT) = 278;
+ (A1 => COUT) = 516;
+ (B1 => COUT) = 516;
+ (C1 => COUT) = 412;
+ (D1 => COUT) = 278;
+ (CIN => COUT) = 43;
+ endspecify
endmodule
// ---------------------------------------
@@ -94,9 +175,14 @@ module TRELLIS_RAM16X2 (
endmodule
// ---------------------------------------
-(* abc9_box_id=3, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
module PFUMX (input ALUT, BLUT, C0, output Z);
assign Z = C0 ? ALUT : BLUT;
+ specify
+ (ALUT => Z) = 98;
+ (BLUT => Z) = 98;
+ (C0 => Z) = 151;
+ endspecify
endmodule
// ---------------------------------------
@@ -106,7 +192,6 @@ module TRELLIS_DPR16X4 (
input WRE,
input WCK,
input [3:0] RAD,
- /* (* abc9_arrival=<TODO> *) */
output [3:0] DO
);
parameter WCKMUX = "WCK";
diff --git a/techlibs/ecp5/ecp5_ffinit.cc b/techlibs/ecp5/ecp5_ffinit.cc
index dbd16cac9..e85bee64e 100644
--- a/techlibs/ecp5/ecp5_ffinit.cc
+++ b/techlibs/ecp5/ecp5_ffinit.cc
@@ -63,11 +63,11 @@ struct Ecp5FfinitPass : public Pass {
for (auto wire : module->selected_wires())
{
- if (wire->attributes.count("\\init") == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
init_wires.insert(wire);
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
@@ -94,11 +94,11 @@ struct Ecp5FfinitPass : public Pass {
}
for (auto cell : module->selected_cells())
{
- if (cell->type != "\\TRELLIS_FF")
+ if (cell->type != ID(TRELLIS_FF))
continue;
- SigSpec sig_d = cell->getPort("\\DI");
- SigSpec sig_q = cell->getPort("\\Q");
- SigSpec sig_lsr = cell->getPort("\\LSR");
+ SigSpec sig_d = cell->getPort(ID(DI));
+ SigSpec sig_q = cell->getPort(ID::Q);
+ SigSpec sig_lsr = cell->getPort(ID(LSR));
if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
continue;
@@ -107,8 +107,8 @@ struct Ecp5FfinitPass : public Pass {
SigBit bit_q = sigmap(sig_q[0]);
std::string regset = "RESET";
- if (cell->hasParam("\\REGSET"))
- regset = cell->getParam("\\REGSET").decode_string();
+ if (cell->hasParam(ID(REGSET)))
+ regset = cell->getParam(ID(REGSET)).decode_string();
State resetState;
if (regset == "SET")
resetState = State::S1;
@@ -136,8 +136,8 @@ struct Ecp5FfinitPass : public Pass {
if (GetSize(sig_lsr) >= 1 && sig_lsr[0] != State::S0) {
std::string srmode = "LSR_OVER_CE";
- if (cell->hasParam("\\SRMODE"))
- srmode = cell->getParam("\\SRMODE").decode_string();
+ if (cell->hasParam(ID(SRMODE)))
+ srmode = cell->getParam(ID(SRMODE)).decode_string();
if (srmode == "ASYNC") {
log("Async reset value %c for FF cell %s inconsistent with init value %c.\n",
resetState != State::S0 ? '1' : '0', log_id(cell), val != State::S0 ? '1' : '0');
@@ -150,14 +150,14 @@ struct Ecp5FfinitPass : public Pass {
module->addOrGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
}
- cell->setPort("\\DI", new_bit_d);
- cell->setPort("\\LSR", State::S0);
+ cell->setPort(ID(DI), new_bit_d);
+ cell->setPort(ID(LSR), State::S0);
- if(cell->hasPort("\\CE")) {
+ if(cell->hasPort(ID(CE))) {
std::string cemux = "CE";
- if (cell->hasParam("\\CEMUX"))
- cemux = cell->getParam("\\CEMUX").decode_string();
- SigSpec sig_ce = cell->getPort("\\CE");
+ if (cell->hasParam(ID(CEMUX)))
+ cemux = cell->getParam(ID(CEMUX)).decode_string();
+ SigSpec sig_ce = cell->getPort(ID(CE));
if (GetSize(sig_ce) >= 1) {
SigBit bit_ce = sigmap(sig_ce[0]);
Wire *new_bit_ce = module->addWire(NEW_ID);
@@ -165,25 +165,25 @@ struct Ecp5FfinitPass : public Pass {
module->addAndnotGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
else
module->addOrGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
- cell->setPort("\\CE", new_bit_ce);
+ cell->setPort(ID(CE), new_bit_ce);
}
}
- cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
+ cell->setParam(ID(REGSET), val != State::S0 ? Const("SET") : Const("RESET"));
handled_initbits.insert(bit_q);
}
} else {
- cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
+ cell->setParam(ID(REGSET), val != State::S0 ? Const("SET") : Const("RESET"));
handled_initbits.insert(bit_q);
}
}
for (auto wire : init_wires)
{
- if (wire->attributes.count("\\init") == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
- Const &initval = wire->attributes.at("\\init");
+ Const &initval = wire->attributes.at(ID::init);
bool remove_attribute = true;
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
@@ -194,7 +194,7 @@ struct Ecp5FfinitPass : public Pass {
}
if (remove_attribute)
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
}
}
}
diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc
index 2bc714b6f..d1503f71f 100644
--- a/techlibs/ecp5/ecp5_gsr.cc
+++ b/techlibs/ecp5/ecp5_gsr.cc
@@ -85,7 +85,7 @@ struct Ecp5GsrPass : public Pass {
continue;
bool gsren = found_gsr;
- if (cell->get_bool_attribute("\\nogsr"))
+ if (cell->get_bool_attribute(ID(nogsr)))
gsren = false;
cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED"));
@@ -102,7 +102,7 @@ struct Ecp5GsrPass : public Pass {
{
if (cell->type != ID($_NOT_))
continue;
- SigSpec sig_a = cell->getPort(ID(A)), sig_y = cell->getPort(ID(Y));
+ SigSpec sig_a = cell->getPort(ID::A), sig_y = cell->getPort(ID::Y);
if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1)
continue;
SigBit a = sigmap(sig_a[0]);
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 793ea15aa..6f5790a14 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -230,7 +230,7 @@ struct SynthEcp5Pass : public ScriptPass
{
if (check_label("begin"))
{
- run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
+ run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
@@ -324,11 +324,11 @@ struct SynthEcp5Pass : public ScriptPass
run("techmap " + techmap_args);
if (abc9) {
- run("read_verilog -icells -lib +/ecp5/abc9_model.v");
+ run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
if (nowidelut)
- run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
+ run("abc9 -maxlut 4 -W 200");
else
- run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
+ run("abc9 -W 200");
run("techmap -map +/ecp5/abc9_unmap.v");
} else {
if (nowidelut)
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-23 12:55:44 +0000