diff options
Diffstat (limited to 'techlibs/efinix')
| -rw-r--r-- | techlibs/efinix/Makefile.inc | 2 | ||||
| -rw-r--r-- | techlibs/efinix/arith_map.v | 4 | ||||
| -rw-r--r-- | techlibs/efinix/cells_map.v | 66 | ||||
| -rw-r--r-- | techlibs/efinix/cells_sim.v | 6 | ||||
| -rw-r--r-- | techlibs/efinix/efinix_fixcarry.cc | 2 | ||||
| -rw-r--r-- | techlibs/efinix/efinix_gbuf.cc | 119 | ||||
| -rw-r--r-- | techlibs/efinix/gbuf_map.v | 3 | ||||
| -rw-r--r-- | techlibs/efinix/synth_efinix.cc | 10 |
8 files changed, 70 insertions, 142 deletions
diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc index 69665982c..2a3a953e3 100644 --- a/techlibs/efinix/Makefile.inc +++ b/techlibs/efinix/Makefile.inc @@ -1,10 +1,10 @@ OBJS += techlibs/efinix/synth_efinix.o -OBJS += techlibs/efinix/efinix_gbuf.o OBJS += techlibs/efinix/efinix_fixcarry.o $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v)) +$(eval $(call add_share_file,share/efinix,techlibs/efinix/gbuf_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/brams.txt)) diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v index 4dac360b9..6bda0505c 100644 --- a/techlibs/efinix/arith_map.v +++ b/techlibs/efinix/arith_map.v @@ -1,8 +1,8 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com> - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2018 Miodrag Milanovic <micko@yosyshq.com> + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v index 1090f8b27..6f6271da2 100644 --- a/techlibs/efinix/cells_map.v +++ b/techlibs/efinix/cells_map.v @@ -1,21 +1,59 @@ -module \$_DFF_N_ (input D, C, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(1'b0), .Q(Q)); endmodule -module \$_DFF_P_ (input D, C, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(1'b0), .Q(Q)); endmodule +(* techmap_celltype = "$_DFFE_[PN][PN][01][PN]_" *) +module \$_DFFE_xxxx_ (input D, C, R, E, output Q); -module \$_DFFE_NN_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b0), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule -module \$_DFFE_NP_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule + parameter _TECHMAP_CELLTYPE_ = ""; -module \$_DFFE_PN_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b0), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule -module \$_DFFE_PP_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule + EFX_FF #( + .CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"), + .CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"), + .SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"), + .D_POLARITY(1'b1), + .SR_SYNC(1'b0), + .SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"), + .SR_SYNC_PRIORITY(1'b1) + ) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q)); -module \$_DFF_NN0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; -module \$_DFF_NP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule -module \$_DFF_NP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule -module \$_DFF_PP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +endmodule + +(* techmap_celltype = "$_SDFFE_[PN][PN][01][PN]_" *) +module \$_SDFFE_xxxx_ (input D, C, R, E, output Q); + + parameter _TECHMAP_CELLTYPE_ = ""; + + EFX_FF #( + .CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"), + .CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"), + .SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"), + .D_POLARITY(1'b1), + .SR_SYNC(1'b1), + .SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"), + .SR_SYNC_PRIORITY(1'b1) + ) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q)); + + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + +endmodule + +(* techmap_celltype = "$_SDFFCE_[PN][PN][01][PN]_" *) +module \$_SDFFCE_xxxx_ (input D, C, R, E, output Q); + + parameter _TECHMAP_CELLTYPE_ = ""; + + EFX_FF #( + .CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"), + .CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"), + .SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"), + .D_POLARITY(1'b1), + .SR_SYNC(1'b1), + .SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"), + .SR_SYNC_PRIORITY(1'b0) + ) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q)); + + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + +endmodule module \$_DLATCH_N_ (E, D, Q); wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v index a74d1c571..22c7bc776 100644 --- a/techlibs/efinix/cells_sim.v +++ b/techlibs/efinix/cells_sim.v @@ -36,6 +36,7 @@ module EFX_FF( output reg Q, input D, input CE, + (* clkbuf_sink *) input CLK, input SR ); @@ -100,6 +101,7 @@ endmodule module EFX_GBUFCE( input CE, input I, + (* clkbuf_driver *) output O ); parameter CE_POLARITY = 1'b1; @@ -115,11 +117,13 @@ module EFX_RAM_5K( input [WRITE_WIDTH-1:0] WDATA, input [WRITE_ADDR_WIDTH-1:0] WADDR, input WE, + (* clkbuf_sink *) input WCLK, input WCLKE, output [READ_WIDTH-1:0] RDATA, input [READ_ADDR_WIDTH-1:0] RADDR, input RE, + (* clkbuf_sink *) input RCLK ); parameter READ_WIDTH = 20; @@ -172,4 +176,4 @@ module EFX_RAM_5K( (WRITE_WIDTH == 10) ? 9 : // 512x10 (WRITE_WIDTH == 5) ? 10 : -1; // 1024x5 -endmodule
\ No newline at end of file +endmodule diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc index 486b8e89c..c61fa79b8 100644 --- a/techlibs/efinix/efinix_fixcarry.cc +++ b/techlibs/efinix/efinix_fixcarry.cc @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2019 Miodrag Milanovic <miodrag@symbioticeda.com> + * Copyright (C) 2019 Miodrag Milanovic <micko@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/techlibs/efinix/efinix_gbuf.cc b/techlibs/efinix/efinix_gbuf.cc deleted file mode 100644 index ae191359a..000000000 --- a/techlibs/efinix/efinix_gbuf.cc +++ /dev/null @@ -1,119 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2019 Miodrag Milanovic <miodrag@symbioticeda.com> - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -static void handle_gbufs(Module *module) -{ - SigMap sigmap(module); - - pool<SigBit> clk_bits; - dict<SigBit, SigBit> rewrite_bits; - vector<pair<Cell*, SigBit>> pad_bits; - - for (auto cell : module->cells()) - { - if (cell->type == ID(EFX_FF)) { - for (auto bit : sigmap(cell->getPort(ID::CLK))) - clk_bits.insert(bit); - } - if (cell->type == ID(EFX_RAM_5K)) { - for (auto bit : sigmap(cell->getPort(ID(RCLK)))) - clk_bits.insert(bit); - for (auto bit : sigmap(cell->getPort(ID(WCLK)))) - clk_bits.insert(bit); - } - } - - for (auto wire : vector<Wire*>(module->wires())) - { - if (!wire->port_input) - continue; - - for (int index = 0; index < GetSize(wire); index++) - { - SigBit bit(wire, index); - SigBit canonical_bit = sigmap(bit); - - if (!clk_bits.count(canonical_bit)) - continue; - - Cell *c = module->addCell(NEW_ID, ID(EFX_GBUFCE)); - SigBit new_bit = module->addWire(NEW_ID); - c->setParam(ID(CE_POLARITY), State::S1); - c->setPort(ID::O, new_bit); - c->setPort(ID(CE), State::S1); - pad_bits.push_back(make_pair(c, bit)); - rewrite_bits[canonical_bit] = new_bit; - - log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit)); - } - } - - auto rewrite_function = [&](SigSpec &s) { - for (auto &bit : s) { - SigBit canonical_bit = sigmap(bit); - if (rewrite_bits.count(canonical_bit)) - bit = rewrite_bits.at(canonical_bit); - } - }; - - module->rewrite_sigspecs(rewrite_function); - - for (auto &it : pad_bits) - it.first->setPort(ID::I, it.second); -} - -struct EfinixGbufPass : public Pass { - EfinixGbufPass() : Pass("efinix_gbuf", "Efinix: insert global clock buffers") { } - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" efinix_gbuf [options] [selection]\n"); - log("\n"); - log("Add Efinix global clock buffers to top module as needed.\n"); - log("\n"); - } - void execute(std::vector<std::string> args, RTLIL::Design *design) override - { - log_header(design, "Executing efinix_gbuf pass (insert global clock buffers).\n"); - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - break; - } - extra_args(args, argidx, design); - - Module *module = design->top_module(); - - if (module == nullptr) - log_cmd_error("No top module found.\n"); - - handle_gbufs(module); - } -} EfinixGbufPass; - -PRIVATE_NAMESPACE_END diff --git a/techlibs/efinix/gbuf_map.v b/techlibs/efinix/gbuf_map.v new file mode 100644 index 000000000..43e0c9ac3 --- /dev/null +++ b/techlibs/efinix/gbuf_map.v @@ -0,0 +1,3 @@ +module \$__EFX_GBUF (input I, output O); + EFX_GBUFCE #(.CE_POLARITY(1'b1)) _TECHMAP_REPLACE_ (.I(I), .O(O), .CE(1'b1)); +endmodule diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index 6ca44eed1..ace56bee9 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -1,8 +1,8 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2019 Miodrag Milanovic <miodrag@symbioticeda.com> - * Copyright (C) 2019 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2019 Miodrag Milanovic <micko@yosyshq.com> + * Copyright (C) 2019 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -182,8 +182,8 @@ struct SynthEfinixPass : public ScriptPass if (check_label("map_ffs")) { + run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x"); run("techmap -D NO_LUT -map +/efinix/cells_map.v"); - run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit"); run("opt_expr -mux_undef"); run("simplemap"); } @@ -202,7 +202,8 @@ struct SynthEfinixPass : public ScriptPass if (check_label("map_gbuf")) { - run("efinix_gbuf"); + run("clkbufmap -buf $__EFX_GBUF O:I"); + run("techmap -map +/efinix/gbuf_map.v"); run("efinix_fixcarry"); run("clean"); } @@ -212,6 +213,7 @@ struct SynthEfinixPass : public ScriptPass run("hierarchy -check"); run("stat"); run("check -noinit"); + run("blackbox =A:whitebox"); } if (check_label("edif")) |