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-rw-r--r--techlibs/fabulous/Makefile.inc10
-rw-r--r--techlibs/fabulous/cells_map.v29
-rw-r--r--techlibs/fabulous/ff_map.v9
-rw-r--r--techlibs/fabulous/io_map.v8
-rw-r--r--techlibs/fabulous/latches_map.v11
-rw-r--r--techlibs/fabulous/prims.v417
-rw-r--r--techlibs/fabulous/ram_regfile.txt46
-rw-r--r--techlibs/fabulous/regfile_map.v42
-rw-r--r--techlibs/fabulous/synth_fabulous.cc396
9 files changed, 968 insertions, 0 deletions
diff --git a/techlibs/fabulous/Makefile.inc b/techlibs/fabulous/Makefile.inc
new file mode 100644
index 000000000..44d57542b
--- /dev/null
+++ b/techlibs/fabulous/Makefile.inc
@@ -0,0 +1,10 @@
+
+OBJS += techlibs/fabulous/synth_fabulous.o
+
+$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/cells_map.v))
+$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/prims.v))
+$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/latches_map.v))
+$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ff_map.v))
+$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ram_regfile.txt))
+$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/regfile_map.v))
+$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/io_map.v))
diff --git a/techlibs/fabulous/cells_map.v b/techlibs/fabulous/cells_map.v
new file mode 100644
index 000000000..eadd18b6f
--- /dev/null
+++ b/techlibs/fabulous/cells_map.v
@@ -0,0 +1,29 @@
+module \$lut (A, Y);
+ parameter WIDTH = 0;
+ parameter LUT = 0;
+
+ input [WIDTH-1:0] A;
+ output Y;
+
+ generate
+ if (WIDTH == 1) begin
+ LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));
+
+ end else
+ if (WIDTH == 2) begin
+ LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));
+
+ end else
+ if (WIDTH == 3) begin
+ LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
+
+ end else
+ if (WIDTH == 4) begin
+ LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
+ end else begin
+ wire _TECHMAP_FAIL_ = 1;
+ end
+ endgenerate
+endmodule
+
+module \$_DFF_P_ (input D, C, output Q); LUTFF _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C)); endmodule
diff --git a/techlibs/fabulous/ff_map.v b/techlibs/fabulous/ff_map.v
new file mode 100644
index 000000000..0a03bd692
--- /dev/null
+++ b/techlibs/fabulous/ff_map.v
@@ -0,0 +1,9 @@
+module \$_DFF_P_ (input D, C, output Q); LUTFF _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C)); endmodule
+
+module \$_DFFE_PP_ (input D, C, E, output Q); LUTFF_E _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E)); endmodule
+
+module \$_SDFF_PP0_ (input D, C, R, output Q); LUTFF_SR _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .R(R)); endmodule
+module \$_SDFF_PP1_ (input D, C, R, output Q); LUTFF_SS _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .S(R)); endmodule
+
+module \$_SDFFCE_PP0P_ (input D, C, E, R, output Q); LUTFF_ESR _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E), .R(R)); endmodule
+module \$_SDFFCE_PP1P_ (input D, C, E, R, output Q); LUTFF_ESS _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E), .S(R)); endmodule
diff --git a/techlibs/fabulous/io_map.v b/techlibs/fabulous/io_map.v
new file mode 100644
index 000000000..c1d4160f8
--- /dev/null
+++ b/techlibs/fabulous/io_map.v
@@ -0,0 +1,8 @@
+module \$__FABULOUS_IBUF (input PAD, output O);
+ IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .O(O), .T(1'b1));
+endmodule
+
+module \$__FABULOUS_OBUF (output PAD, input I);
+ IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .I(I), .T(1'b0));
+endmodule
+
diff --git a/techlibs/fabulous/latches_map.v b/techlibs/fabulous/latches_map.v
new file mode 100644
index 000000000..c28f88cf7
--- /dev/null
+++ b/techlibs/fabulous/latches_map.v
@@ -0,0 +1,11 @@
+module \$_DLATCH_N_ (E, D, Q);
+ wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+ input E, D;
+ output Q = !E ? D : Q;
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+ wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+ input E, D;
+ output Q = E ? D : Q;
+endmodule
diff --git a/techlibs/fabulous/prims.v b/techlibs/fabulous/prims.v
new file mode 100644
index 000000000..8ddae5beb
--- /dev/null
+++ b/techlibs/fabulous/prims.v
@@ -0,0 +1,417 @@
+module LUT1(output O, input I0);
+ parameter [1:0] INIT = 0;
+ assign O = I0 ? INIT[1] : INIT[0];
+endmodule
+
+module LUT2(output O, input I0, I1);
+ parameter [3:0] INIT = 0;
+ wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
+ assign O = I0 ? s1[1] : s1[0];
+endmodule
+
+module LUT3(output O, input I0, I1, I2);
+ parameter [7:0] INIT = 0;
+ wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
+ wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
+ assign O = I0 ? s1[1] : s1[0];
+endmodule
+
+module LUT4(output O, input I0, I1, I2, I3);
+ parameter [15:0] INIT = 0;
+ wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
+ wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
+ wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
+ assign O = I0 ? s1[1] : s1[0];
+endmodule
+
+module LUTFF(input CLK, D, output reg O);
+ initial O = 1'b0;
+ always @ (posedge CLK) begin
+ O <= D;
+ end
+endmodule
+
+module FABULOUS_MUX2(input I0, I1, S0, output O);
+ assign O = S0 ? I1 : I0;
+endmodule
+
+module FABULOUS_MUX4(input I0, I1, I2, I3, S0, S1, output O);
+ wire A0 = S0 ? I1 : I0;
+ wire A1 = S0 ? I3 : I2;
+ assign O = S1 ? A1 : A0;
+endmodule
+
+module FABULOUS_MUX8(input I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2, output O);
+ wire A0 = S0 ? I1 : I0;
+ wire A1 = S0 ? I3 : I2;
+ wire A2 = S0 ? I5 : I4;
+ wire A3 = S0 ? I7 : I6;
+ wire B0 = S1 ? A1 : A0;
+ wire B1 = S1 ? A3 : A2;
+ assign O = S2 ? B1 : B0;
+endmodule
+
+module FABULOUS_LC #(
+ parameter K = 4,
+ parameter [2**K-1:0] INIT = 0,
+ parameter DFF_ENABLE = 1'b0
+) (
+ input CLK,
+ input [K-1:0] I,
+ output O,
+ output Q
+);
+ wire f_wire;
+
+ //LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
+ generate
+ if (K == 1) begin
+ LUT1 #(.INIT(INIT)) lut1 (.O(f_wire), .I0(I[0]));
+ end else
+ if (K == 2) begin
+ LUT2 #(.INIT(INIT)) lut2 (.O(f_wire), .I0(I[0]), .I1(I[1]));
+ end else
+ if (K == 3) begin
+ LUT3 #(.INIT(INIT)) lut3 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]));
+ end else
+ if (K == 4) begin
+ LUT4 #(.INIT(INIT)) lut4 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3]));
+ end
+ endgenerate
+
+ LUTFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
+
+ assign O = f_wire;
+endmodule
+
+(* blackbox *)
+module Global_Clock (output CLK);
+`ifndef SYNTHESIS
+ initial CLK = 0;
+ always #10 CLK = ~CLK;
+`endif
+endmodule
+
+(* blackbox, keep *)
+module InPass4_frame_config (output O0, O1, O2, O3);
+
+endmodule
+
+
+(* blackbox, keep *)
+module OutPass4_frame_config (input I0, I1, I2, I3);
+
+endmodule
+
+(* keep *)
+module IO_1_bidirectional_frame_config_pass (input CLK, T, I, output Q, O, (* iopad_external_pin *) inout PAD);
+ assign PAD = T ? 1'bz : I;
+ assign O = PAD;
+ reg Q_q;
+ always @(posedge CLK) Q_q <= O;
+ assign Q = Q_q;
+endmodule
+
+
+module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, Q19, Q18, Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, clr, CLK);
+ parameter A_reg = 1'b0;
+ parameter B_reg = 1'b0;
+ parameter C_reg = 1'b0;
+ parameter ACC = 1'b0;
+ parameter signExtension = 1'b0;
+ parameter ACCout = 1'b0;
+
+ //parameter NoConfigBits = 6;// has to be adjusted manually (we don't use an arithmetic parser for the value)
+ // IMPORTANT: this has to be in a dedicated line
+ input A7;// operand A
+ input A6;
+ input A5;
+ input A4;
+ input A3;
+ input A2;
+ input A1;
+ input A0;
+ input B7;// operand B
+ input B6;
+ input B5;
+ input B4;
+ input B3;
+ input B2;
+ input B1;
+ input B0;
+ input C19;// operand C
+ input C18;
+ input C17;
+ input C16;
+ input C15;
+ input C14;
+ input C13;
+ input C12;
+ input C11;
+ input C10;
+ input C9;
+ input C8;
+ input C7;
+ input C6;
+ input C5;
+ input C4;
+ input C3;
+ input C2;
+ input C1;
+ input C0;
+ output Q19;// result
+ output Q18;
+ output Q17;
+ output Q16;
+ output Q15;
+ output Q14;
+ output Q13;
+ output Q12;
+ output Q11;
+ output Q10;
+ output Q9;
+ output Q8;
+ output Q7;
+ output Q6;
+ output Q5;
+ output Q4;
+ output Q3;
+ output Q2;
+ output Q1;
+ output Q0;
+
+ input clr;
+ input CLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
+ // GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
+
+
+ wire [7:0] A; // port A read data
+ wire [7:0] B; // port B read data
+ wire [19:0] C; // port B read data
+ reg [7:0] A_q; // port A read data register
+ reg [7:0] B_q; // port B read data register
+ reg [19:0] C_q; // port B read data register
+ wire [7:0] OPA; // port A
+ wire [7:0] OPB; // port B
+ wire [19:0] OPC; // port B
+ reg [19:0] ACC_data ; // accumulator register
+ wire [19:0] sum;// port B read data register
+ wire [19:0] sum_in;// port B read data register
+ wire [15:0] product;
+ wire [19:0] product_extended;
+
+ assign A = {A7,A6,A5,A4,A3,A2,A1,A0};
+ assign B = {B7,B6,B5,B4,B3,B2,B1,B0};
+ assign C = {C19,C18,C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0};
+
+ assign OPA = A_reg ? A_q : A;
+ assign OPB = B_reg ? B_q : B;
+ assign OPC = C_reg ? C_q : C;
+
+ assign sum_in = ACC ? ACC_data : OPC;// we can
+
+ assign product = OPA * OPB;
+
+// The sign extension was not tested
+ assign product_extended = signExtension ? {product[15],product[15],product[15],product[15],product} : {4'b0000,product};
+
+ assign sum = product_extended + sum_in;
+
+ assign Q19 = ACCout ? ACC_data[19] : sum[19];
+ assign Q18 = ACCout ? ACC_data[18] : sum[18];
+ assign Q17 = ACCout ? ACC_data[17] : sum[17];
+ assign Q16 = ACCout ? ACC_data[16] : sum[16];
+ assign Q15 = ACCout ? ACC_data[15] : sum[15];
+ assign Q14 = ACCout ? ACC_data[14] : sum[14];
+ assign Q13 = ACCout ? ACC_data[13] : sum[13];
+ assign Q12 = ACCout ? ACC_data[12] : sum[12];
+ assign Q11 = ACCout ? ACC_data[11] : sum[11];
+ assign Q10 = ACCout ? ACC_data[10] : sum[10];
+ assign Q9 = ACCout ? ACC_data[9] : sum[9];
+ assign Q8 = ACCout ? ACC_data[8] : sum[8];
+ assign Q7 = ACCout ? ACC_data[7] : sum[7];
+ assign Q6 = ACCout ? ACC_data[6] : sum[6];
+ assign Q5 = ACCout ? ACC_data[5] : sum[5];
+ assign Q4 = ACCout ? ACC_data[4] : sum[4];
+ assign Q3 = ACCout ? ACC_data[3] : sum[3];
+ assign Q2 = ACCout ? ACC_data[2] : sum[2];
+ assign Q1 = ACCout ? ACC_data[1] : sum[1];
+ assign Q0 = ACCout ? ACC_data[0] : sum[0];
+
+ always @ (posedge CLK)
+ begin
+ A_q <= A;
+ B_q <= B;
+ C_q <= C;
+ if (clr == 1'b1) begin
+ ACC_data <= 20'b00000000000000000000;
+ end else begin
+ ACC_data <= sum;
+ end
+ end
+
+endmodule
+
+module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_en, AD0, AD1, AD2, AD3, A_ADR0, A_ADR1, A_ADR2, A_ADR3, A_ADR4, BD0, BD1, BD2, BD3, B_ADR0, B_ADR1, B_ADR2, B_ADR3, B_ADR4, CLK);
+ //parameter NoConfigBits = 2;// has to be adjusted manually (we don't use an arithmetic parser for the value)
+ parameter AD_reg = 1'b0;
+ parameter BD_reg = 1'b0;
+ // IMPORTANT: this has to be in a dedicated line
+ input D0; // Register File write port
+ input D1;
+ input D2;
+ input D3;
+ input W_ADR0;
+ input W_ADR1;
+ input W_ADR2;
+ input W_ADR3;
+ input W_ADR4;
+ input W_en;
+
+ output AD0;// Register File read port A
+ output AD1;
+ output AD2;
+ output AD3;
+ input A_ADR0;
+ input A_ADR1;
+ input A_ADR2;
+ input A_ADR3;
+ input A_ADR4;
+
+ output BD0;//Register File read port B
+ output BD1;
+ output BD2;
+ output BD3;
+ input B_ADR0;
+ input B_ADR1;
+ input B_ADR2;
+ input B_ADR3;
+ input B_ADR4;
+
+ input CLK;// EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
+
+ // GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
+
+
+ //type memtype is array (31 downto 0) of std_logic_vector(3 downto 0); // 32 entries of 4 bit
+ //signal mem : memtype := (others => (others => '0'));
+ reg [3:0] mem [31:0];
+
+ wire [4:0] W_ADR;// write address
+ wire [4:0] A_ADR;// port A read address
+ wire [4:0] B_ADR;// port B read address
+
+ wire [3:0] D; // write data
+ wire [3:0] AD; // port A read data
+ wire [3:0] BD; // port B read data
+
+ reg [3:0] AD_q; // port A read data register
+ reg [3:0] BD_q; // port B read data register
+
+ integer i;
+
+ assign W_ADR = {W_ADR4,W_ADR3,W_ADR2,W_ADR1,W_ADR0};
+ assign A_ADR = {A_ADR4,A_ADR3,A_ADR2,A_ADR1,A_ADR0};
+ assign B_ADR = {B_ADR4,B_ADR3,B_ADR2,B_ADR1,B_ADR0};
+
+ assign D = {D3,D2,D1,D0};
+
+ initial begin
+ for (i=0; i<32; i=i+1) begin
+ mem[i] = 4'b0000;
+ end
+ end
+
+ always @ (posedge CLK) begin : P_write
+ if (W_en == 1'b1) begin
+ mem[W_ADR] <= D ;
+ end
+ end
+
+ assign AD = mem[A_ADR];
+ assign BD = mem[B_ADR];
+
+ always @ (posedge CLK) begin
+ AD_q <= AD;
+ BD_q <= BD;
+ end
+
+ assign AD0 = AD_reg ? AD_q[0] : AD[0];
+ assign AD1 = AD_reg ? AD_q[1] : AD[1];
+ assign AD2 = AD_reg ? AD_q[2] : AD[2];
+ assign AD3 = AD_reg ? AD_q[3] : AD[3];
+
+ assign BD0 = BD_reg ? BD_q[0] : BD[0];
+ assign BD1 = BD_reg ? BD_q[1] : BD[1];
+ assign BD2 = BD_reg ? BD_q[2] : BD[2];
+ assign BD3 = BD_reg ? BD_q[3] : BD[3];
+
+endmodule
+
+`ifdef EQUIV
+`define COMPLEX_DFF
+`endif
+
+`ifdef COMPLEX_DFF
+module LUTFF_E (
+ output reg O,
+ input CLK, E, D
+);
+ initial O = 1'b0;
+ always @(posedge CLK)
+ if (E)
+ O <= D;
+endmodule
+
+module LUTFF_SR (
+ output reg O,
+ input CLK, R, D
+);
+ initial O = 1'b0;
+ always @(posedge CLK)
+ if (R)
+ O <= 0;
+ else
+ O <= D;
+endmodule
+
+module LUTFF_SS (
+ output reg O,
+ input CLK, S, D
+);
+ initial O = 1'b0;
+ always @(posedge CLK)
+ if (S)
+ O <= 1;
+ else
+ O <= D;
+endmodule
+
+module LUTFF_ESR (
+ output reg O,
+ input CLK, E, R, D
+);
+ initial O = 1'b0;
+ always @(posedge CLK)
+ if (E) begin
+ if (R)
+ O <= 0;
+ else
+ O <= D;
+ end
+endmodule
+
+module LUTFF_ESS (
+ output reg O,
+ input CLK, E, S, D
+);
+ initial O = 1'b0;
+ always @(posedge CLK)
+ if (E) begin
+ if (S)
+ O <= 1;
+ else
+ O <= D;
+ end
+endmodule
+`endif // COMPLEX_DFF \ No newline at end of file
diff --git a/techlibs/fabulous/ram_regfile.txt b/techlibs/fabulous/ram_regfile.txt
new file mode 100644
index 000000000..af834b005
--- /dev/null
+++ b/techlibs/fabulous/ram_regfile.txt
@@ -0,0 +1,46 @@
+# Yosys doesn't support configurable sync/async ports.
+# So we define three RAMs for 2xasync, 1xsync 1xasync and 2xsync
+
+ram distributed $__REGFILE_AA_ {
+ abits 5;
+ width 4;
+ cost 6;
+ port sw "W" {
+ clock posedge "CLK";
+ }
+ port ar "A" {
+ }
+ port ar "B" {
+ }
+}
+
+ram distributed $__REGFILE_SA_ {
+ abits 5;
+ width 4;
+ cost 5;
+ port sw "W" {
+ clock posedge "CLK";
+ wrtrans all old;
+ }
+ port sr "A" {
+ clock posedge "CLK";
+ }
+ port ar "B" {
+ }
+}
+
+ram distributed $__REGFILE_SS_ {
+ abits 5;
+ width 4;
+ cost 4;
+ port sw "W" {
+ clock posedge "CLK";
+ wrtrans all old;
+ }
+ port sr "A" {
+ clock posedge "CLK";
+ }
+ port sr "B" {
+ clock posedge "CLK";
+ }
+}
diff --git a/techlibs/fabulous/regfile_map.v b/techlibs/fabulous/regfile_map.v
new file mode 100644
index 000000000..14342495e
--- /dev/null
+++ b/techlibs/fabulous/regfile_map.v
@@ -0,0 +1,42 @@
+(* techmap_celltype = "$__REGFILE_[AS][AS]_" *)
+module \$__REGFILE_XX_ (...);
+
+parameter _TECHMAP_CELLTYPE_ = "";
+localparam [0:0] B_SYNC = _TECHMAP_CELLTYPE_[15:8] == "S";
+localparam [0:0] A_SYNC = _TECHMAP_CELLTYPE_[23:16] == "S";
+
+localparam WIDTH = 4;
+localparam ABITS = 5;
+
+input [WIDTH-1:0] PORT_W_WR_DATA;
+input [ABITS-1:0] PORT_W_ADDR;
+input PORT_W_WR_EN;
+
+output [WIDTH-1:0] PORT_A_RD_DATA;
+input [ABITS-1:0] PORT_A_ADDR;
+
+output [WIDTH-1:0] PORT_B_RD_DATA;
+input [ABITS-1:0] PORT_B_ADDR;
+
+// Unused - we have a shared clock - but keep techmap happy
+input PORT_W_CLK;
+input PORT_A_CLK;
+input PORT_B_CLK;
+
+input CLK_CLK;
+
+RegFile_32x4 #(
+ .AD_reg(A_SYNC),
+ .BD_reg(B_SYNC)
+) _TECHMAP_REPLACE_ (
+ .D0(PORT_W_WR_DATA[0]), .D1(PORT_W_WR_DATA[1]), .D2(PORT_W_WR_DATA[2]), .D3(PORT_W_WR_DATA[3]),
+ .W_ADR0(PORT_W_ADDR[0]), .W_ADR1(PORT_W_ADDR[1]), .W_ADR2(PORT_W_ADDR[2]), .W_ADR3(PORT_W_ADDR[3]), .W_ADR4(PORT_W_ADDR[4]),
+ .W_en(PORT_W_WR_EN),
+ .AD0(PORT_A_RD_DATA[0]), .AD1(PORT_A_RD_DATA[1]), .AD2(PORT_A_RD_DATA[2]), .AD3(PORT_A_RD_DATA[3]),
+ .A_ADR0(PORT_A_ADDR[0]), .A_ADR1(PORT_A_ADDR[1]), .A_ADR2(PORT_A_ADDR[2]), .A_ADR3(PORT_A_ADDR[3]), .A_ADR4(PORT_A_ADDR[4]),
+ .BD0(PORT_B_RD_DATA[0]), .BD1(PORT_B_RD_DATA[1]), .BD2(PORT_B_RD_DATA[2]), .BD3(PORT_B_RD_DATA[3]),
+ .B_ADR0(PORT_B_ADDR[0]), .B_ADR1(PORT_B_ADDR[1]), .B_ADR2(PORT_B_ADDR[2]), .B_ADR3(PORT_B_ADDR[3]), .B_ADR4(PORT_B_ADDR[4]),
+ .CLK(CLK_CLK)
+);
+
+endmodule
diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc
new file mode 100644
index 000000000..d7c45e094
--- /dev/null
+++ b/techlibs/fabulous/synth_fabulous.cc
@@ -0,0 +1,396 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthPass : public ScriptPass
+{
+ SynthPass() : ScriptPass("synth_fabulous", "FABulous synthesis script") { }
+
+ void help() override
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" synth_fabulous [options]\n");
+ log("\n");
+ log("This command runs synthesis for FPGA fabrics generated with FABulous. This command does not operate\n");
+ log("on partly selected designs.\n");
+ log("\n");
+ log(" -top <module>\n");
+ log(" use the specified module as top module (default='top')\n");
+ log("\n");
+ log(" -auto-top\n");
+ log(" automatically determine the top of the design hierarchy\n");
+ log("\n");
+ log(" -blif <file>\n");
+ log(" write the design to the specified BLIF file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -edif <file>\n");
+ log(" write the design to the specified EDIF file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -json <file>\n");
+ log(" write the design to the specified JSON file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -lut <k>\n");
+ log(" perform synthesis for a k-LUT architecture (default 4).\n");
+ log("\n");
+ log(" -vpr\n");
+ log(" perform synthesis for the FABulous VPR flow (using slightly different techmapping).\n");
+ log("\n");
+ log(" -plib <primitive_library.v>\n");
+ log(" use the specified Verilog file as a primitive library.\n");
+ log("\n");
+ log(" -extra-plib <primitive_library.v>\n");
+ log(" use the specified Verilog file for extra primitives (can be specified multiple\n");
+ log(" times).\n");
+ log("\n");
+ log(" -extra-map <techamp.v>\n");
+ log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n");
+ log(" times).\n");
+ log("\n");
+ log(" -encfile <file>\n");
+ log(" passed to 'fsm_recode' via 'fsm'\n");
+ log("\n");
+ log(" -nofsm\n");
+ log(" do not run FSM optimization\n");
+ log("\n");
+ log(" -noalumacc\n");
+ log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
+ log(" their direct form ($add, $sub, etc.).\n");
+ log("\n");
+ log(" -noregfile\n");
+ log(" do not map register files\n");
+ log("\n");
+ log(" -iopad\n");
+ log(" enable automatic insertion of IO buffers (otherwise a wrapper\n");
+ log(" with manually inserted and constrained IO should be used.)\n");
+ log("\n");
+ log(" -complex-dff\n");
+ log(" enable support for FFs with enable and synchronous SR (must also be\n");
+ log(" supported by the target fabric.)\n");
+ log("\n");
+ log(" -noflatten\n");
+ log(" do not flatten design after elaboration\n");
+ log("\n");
+ log(" -nordff\n");
+ log(" passed to 'memory'. prohibits merging of FFs into memory read ports\n");
+ log("\n");
+ log(" -noshare\n");
+ log(" do not run SAT-based resource sharing\n");
+ log("\n");
+ log(" -run <from_label>[:<to_label>]\n");
+ log(" only run the commands between the labels (see below). an empty\n");
+ log(" from label is synonymous to 'begin', and empty to label is\n");
+ log(" synonymous to the end of the command list.\n");
+ log("\n");
+ log(" -no-rw-check\n");
+ log(" marks all recognized read ports as \"return don't-care value on\n");
+ log(" read/write collision\" (same result as setting the no_rw_check\n");
+ log(" attribute on all memories).\n");
+ log("\n");
+ log("\n");
+ log("The following commands are executed by this synthesis command:\n");
+ help_script();
+ log("\n");
+ }
+
+ string top_module, json_file, blif_file, plib, fsm_opts, memory_opts;
+ std::vector<string> extra_plib, extra_map;
+
+ bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten;
+ int lut;
+
+ void clear_flags() override
+ {
+ top_module.clear();
+ plib.clear();
+ autotop = false;
+ lut = 4;
+ forvpr = false;
+ noalumacc = false;
+ nofsm = false;
+ noshare = false;
+ iopad = false;
+ complexdff = false;
+ flatten = true;
+ json_file = "";
+ blif_file = "";
+ }
+
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
+ {
+ string run_from, run_to;
+ clear_flags();
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-top" && argidx+1 < args.size()) {
+ top_module = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-json" && argidx+1 < args.size()) {
+ json_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-blif" && argidx+1 < args.size()) {
+ blif_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-run" && argidx+1 < args.size()) {
+ size_t pos = args[argidx+1].find(':');
+ if (pos == std::string::npos) {
+ run_from = args[++argidx];
+ run_to = args[argidx];
+ } else {
+ run_from = args[++argidx].substr(0, pos);
+ run_to = args[argidx].substr(pos+1);
+ }
+ continue;
+ }
+ if (args[argidx] == "-vpr") {
+ forvpr = true;
+ continue;
+ }
+ if (args[argidx] == "-auto-top") {
+ autotop = true;
+ continue;
+ }
+ if (args[argidx] == "-lut") {
+ lut = atoi(args[++argidx].c_str());
+ continue;
+ }
+ if (args[argidx] == "-plib" && argidx+1 < args.size()) {
+ plib = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-extra-plib" && argidx+1 < args.size()) {
+ extra_plib.push_back(args[++argidx]);
+ continue;
+ }
+ if (args[argidx] == "-extra-map" && argidx+1 < args.size()) {
+ extra_map.push_back(args[++argidx]);
+ continue;
+ }
+ if (args[argidx] == "-nofsm") {
+ nofsm = true;
+ continue;
+ }
+ if (args[argidx] == "-noalumacc") {
+ noalumacc = true;
+ continue;
+ }
+ if (args[argidx] == "-nordff") {
+ memory_opts += " -nordff";
+ continue;
+ }
+ if (args[argidx] == "-noshare") {
+ noshare = true;
+ continue;
+ }
+ if (args[argidx] == "-no-rw-check") {
+ memory_opts += " -no-rw-check";
+ continue;
+ }
+ if (args[argidx] == "-noregfile") {
+ noregfile = true;
+ continue;
+ }
+ if (args[argidx] == "-iopad") {
+ iopad = true;
+ continue;
+ }
+ if (args[argidx] == "-complex-dff") {
+ complexdff = true;
+ continue;
+ }
+ if (args[argidx] == "-noflatten") {
+ flatten = false;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (!design->full_selection())
+ log_cmd_error("This command only operates on fully selected designs!\n");
+
+ log_header(design, "Executing SYNTH_FABULOUS pass.\n");
+ log_push();
+
+ run_script(design, run_from, run_to);
+
+ log_pop();
+ }
+
+ void script() override
+ {
+ if (plib.empty())
+ run(stringf("read_verilog %s -lib +/fabulous/prims.v", complexdff ? "-DCOMPLEX_DFF" : ""));
+ else
+ run("read_verilog -lib " + plib);
+
+ if (help_mode) {
+ run("read_verilog -lib <extra_plib.v>", "(for each -extra-plib)");
+ } else for (auto lib : extra_plib) {
+ run("read_verilog -lib " + lib);
+ }
+
+ if (check_label("begin")) {
+ if (top_module.empty()) {
+ if (autotop)
+ run("hierarchy -check -auto-top");
+ else
+ run("hierarchy -check");
+ } else
+ run(stringf("hierarchy -check -top %s", top_module.c_str()));
+ run("proc");
+ }
+
+
+ if (check_label("flatten", "(unless -noflatten)"))
+ {
+ if (flatten) {
+ run("flatten");
+ run("tribuf -logic");
+ run("deminout");
+ }
+ }
+
+ if (check_label("coarse")) {
+ run("tribuf -logic");
+ run("deminout");
+
+ // synth pass
+ run("opt_expr");
+ run("opt_clean");
+ run("check");
+ run("opt -nodffe -nosdff");
+ if (!nofsm)
+ run("fsm" + fsm_opts, " (unless -nofsm)");
+ run("opt");
+ run("wreduce");
+ run("peepopt");
+ run("opt_clean");
+ if (help_mode)
+ run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)");
+ else if (lut)
+ run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut));
+ if (!noalumacc)
+ run("alumacc", " (unless -noalumacc)");
+ if (!noshare)
+ run("share", " (unless -noshare)");
+ run("opt");
+ run("memory -nomap" + memory_opts);
+ run("opt_clean");
+ }
+
+ if (check_label("map_ram")) {
+ // RegFile extraction
+ if (!noregfile) {
+ run("memory_libmap -lib +/fabulous/ram_regfile.txt");
+ run("techmap -map +/fabulous/regfile_map.v");
+ }
+ }
+
+ if (check_label("map_ffram")) {
+ run("opt -fast -mux_undef -undriven -fine");
+ run("memory_map");
+ run("opt -undriven -fine");
+ }
+
+ if (check_label("map_gates")) {
+ run("opt -full");
+ run("techmap -map +/techmap.v");
+ run("opt -fast");
+ }
+
+ if (check_label("map_iopad", "(if -iopad)")) {
+ if (iopad) {
+ run("opt -full");
+ run("iopadmap -bits -outpad $__FABULOUS_OBUF I:PAD -inpad $__FABULOUS_IBUF O:PAD "
+ "-toutpad IO_1_bidirectional_frame_config_pass ~T:I:PAD "
+ "-tinoutpad IO_1_bidirectional_frame_config_pass ~T:O:I:PAD A:top", "(skip if '-noiopad')");
+ run("techmap -map +/fabulous/io_map.v");
+ }
+ }
+
+
+ if (check_label("map_ffs")) {
+ if (complexdff) {
+ run("dfflegalize -cell $_DFF_P_ 0 -cell $_SDFF_PP?_ 0 -cell $_SDFFCE_PP?P_ 0 -cell $_DLATCH_?_ x", "with -complex-dff");
+ } else {
+ run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff");
+ }
+ run("techmap -map +/fabulous/latches_map.v");
+ run("techmap -map +/fabulous/ff_map.v");
+ if (help_mode) {
+ run("techmap -map <extra_map.v>...", "(for each -extra-map)");
+ } else if (!extra_map.empty()) {
+ std::string map_str = "techmap";
+ for (auto map : extra_map)
+ map_str += stringf(" -map %s", map.c_str());
+ run(map_str);
+ }
+ run("clean");
+ }
+
+ if (check_label("map_luts")) {
+ run(stringf("abc -lut %d -dress", lut));
+ run("clean");
+ }
+
+ if (check_label("map_cells")) {
+ if (!forvpr)
+ run(stringf("techmap -D LUT_K=%d -map +/fabulous/cells_map.v", lut));
+ run("clean");
+ }
+ if (check_label("check")) {
+ run("hierarchy -check");
+ run("stat");
+ }
+
+ if (check_label("blif"))
+ {
+ if (!blif_file.empty() || help_mode)
+ {
+ run("opt_clean -purge");
+ run(stringf("write_blif -attr -cname -conn -param %s",
+ help_mode ? "<file-name>" : blif_file.c_str()));
+ }
+ }
+
+ if (check_label("json"))
+ {
+ if (!json_file.empty() || help_mode)
+ run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+ }
+ }
+} SynthPass;
+
+PRIVATE_NAMESPACE_END
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 17:37:20 +0000