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-rw-r--r--techlibs/gowin/synth_gowin.cc133
1 files changed, 114 insertions, 19 deletions
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 44dec265d..c5b41b503 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -29,7 +29,7 @@ struct SynthGowinPass : public ScriptPass
{
SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
- virtual void help() YS_OVERRIDE
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -49,8 +49,29 @@ struct SynthGowinPass : public ScriptPass
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
+ log(" -nodffe\n");
+ log(" do not use flipflops with CE in output netlist\n");
+ log("\n");
+ log(" -nobram\n");
+ log(" do not use BRAM cells in output netlist\n");
+ log("\n");
+ log(" -nolutram\n");
+ log(" do not use distributed RAM cells in output netlist\n");
+ log("\n");
+ log(" -noflatten\n");
+ log(" do not flatten design before synthesis\n");
+ log("\n");
log(" -retime\n");
- log(" run 'abc' with -dff option\n");
+ log(" run 'abc' with '-dff -D 1' options\n");
+ log("\n");
+ log(" -nowidelut\n");
+ log(" do not use muxes to implement LUTs larger than LUT4s\n");
+ log("\n");
+ log(" -noiopads\n");
+ log(" do not emit IOB at top level ports\n");
+ //log("\n");
+ //log(" -abc9\n");
+ //log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@@ -59,16 +80,23 @@ struct SynthGowinPass : public ScriptPass
}
string top_opt, vout_file;
- bool retime;
+ bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads;
- virtual void clear_flags() YS_OVERRIDE
+ void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
vout_file = "";
retime = false;
+ flatten = true;
+ nobram = false;
+ nodffe = false;
+ nolutram = false;
+ nowidelut = false;
+ abc9 = false;
+ noiopads = false;
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@@ -96,12 +124,40 @@ struct SynthGowinPass : public ScriptPass
retime = true;
continue;
}
+ if (args[argidx] == "-nobram") {
+ nobram = true;
+ continue;
+ }
+ if (args[argidx] == "-nolutram" || /*deprecated*/args[argidx] == "-nodram") {
+ nolutram = true;
+ continue;
+ }
+ if (args[argidx] == "-nodffe") {
+ nodffe = true;
+ continue;
+ }
+ if (args[argidx] == "-noflatten") {
+ flatten = false;
+ continue;
+ }
+ if (args[argidx] == "-nowidelut") {
+ nowidelut = true;
+ continue;
+ }
+ //if (args[argidx] == "-abc9") {
+ // abc9 = true;
+ // continue;
+ //}
+ if (args[argidx] == "-noiopads") {
+ noiopads = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
if (!design->full_selection())
- log_cmd_error("This comannd only operates on fully selected designs!\n");
+ log_cmd_error("This command only operates on fully selected designs!\n");
log_header(design, "Executing SYNTH_GOWIN pass.\n");
log_push();
@@ -111,7 +167,7 @@ struct SynthGowinPass : public ScriptPass
log_pop();
}
- virtual void script() YS_OVERRIDE
+ void script() YS_OVERRIDE
{
if (check_label("begin"))
{
@@ -119,7 +175,7 @@ struct SynthGowinPass : public ScriptPass
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
- if (check_label("flatten"))
+ if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc");
run("flatten");
@@ -132,31 +188,70 @@ struct SynthGowinPass : public ScriptPass
run("synth -run coarse");
}
- if (check_label("fine"))
+ if (!nobram && check_label("map_bram", "(skip if -nobram)"))
+ {
+ run("memory_bram -rules +/gowin/brams.txt");
+ run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
+ }
+
+ if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
+ {
+ run("memory_bram -rules +/gowin/lutrams.txt");
+ run("techmap -map +/gowin/lutrams_map.v");
+ run("determine_init");
+ }
+
+ if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
- run("techmap");
- run("clean -purge");
- run("splitnets -ports");
- run("setundef -undriven -zero");
+ }
+
+ if (check_label("map_gates"))
+ {
+ run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
+ run("techmap -map +/techmap.v");
if (retime || help_mode)
- run("abc -dff", "(only if -retime)");
+ run("abc -dff -D 1", "(only if -retime)");
+ run("splitnets");
+ }
+
+ if (check_label("map_ffs"))
+ {
+ run("dffsr2dff");
+ run("dff2dffs -match-init");
+ run("opt_clean");
+ if (!nodffe)
+ run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
+ run("techmap -map +/gowin/cells_map.v");
+ run("opt_expr -mux_undef");
+ run("simplemap");
}
if (check_label("map_luts"))
{
- run("abc -lut 4");
+ /*if (nowidelut && abc9) {
+ run("abc9 -lut 4");
+ } else*/ if (nowidelut && !abc9) {
+ run("abc -lut 4");
+ } else /*if (!nowidelut && abc9) {
+ run("abc9 -lut 4:8");
+ } else*/ if (!nowidelut && !abc9) {
+ run("abc -lut 4:8");
+ }
run("clean");
}
if (check_label("map_cells"))
{
run("techmap -map +/gowin/cells_map.v");
- run("hilomap -hicell VCC V -locell GND G");
- run("iopadmap -inpad IBUF O:I -outpad OBUF I:O");
- run("clean -purge");
+ run("setundef -undriven -params -zero");
+ run("hilomap -singleton -hicell VCC V -locell GND G");
+ if (!noiopads || help_mode)
+ run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
+ "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)");
+ run("clean");
}
if (check_label("check"))
@@ -169,7 +264,7 @@ struct SynthGowinPass : public ScriptPass
if (check_label("vout"))
{
if (!vout_file.empty() || help_mode)
- run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix gen %s",
+ run(stringf("write_verilog -decimal -attr2comment -defparam -renameprefix gen %s",
help_mode ? "<file-name>" : vout_file.c_str()));
}
}