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-rw-r--r--techlibs/gowin/synth_gowin.cc87
1 files changed, 60 insertions, 27 deletions
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 32d9cc0a5..cfbc9b9a6 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -44,6 +44,11 @@ struct SynthGowinPass : public ScriptPass
log(" write the design to the specified Verilog netlist file. writing of an\n");
log(" output file is omitted if this parameter is not specified.\n");
log("\n");
+ log(" -json <file>\n");
+ log(" write the design to the specified JSON netlist file. writing of an\n");
+ log(" output file is omitted if this parameter is not specified.\n");
+ log(" This disables features not yet supported by nexpnr-gowin.\n");
+ log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
@@ -69,9 +74,12 @@ struct SynthGowinPass : public ScriptPass
log("\n");
log(" -noiopads\n");
log(" do not emit IOB at top level ports\n");
- //log("\n");
- //log(" -abc9\n");
- //log(" use new ABC9 flow (EXPERIMENTAL)\n");
+ log("\n");
+ log(" -noalu\n");
+ log(" do not use ALU cells\n");
+ log("\n");
+ log(" -abc9\n");
+ log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@@ -79,13 +87,14 @@ struct SynthGowinPass : public ScriptPass
log("\n");
}
- string top_opt, vout_file;
- bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads;
+ string top_opt, vout_file, json_file;
+ bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads, noalu;
void clear_flags() override
{
top_opt = "-auto-top";
vout_file = "";
+ json_file = "";
retime = false;
flatten = true;
nobram = false;
@@ -94,6 +103,7 @@ struct SynthGowinPass : public ScriptPass
nowidelut = false;
abc9 = false;
noiopads = false;
+ noalu = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -112,6 +122,12 @@ struct SynthGowinPass : public ScriptPass
vout_file = args[++argidx];
continue;
}
+ if (args[argidx] == "-json" && argidx+1 < args.size()) {
+ json_file = args[++argidx];
+ nobram = true;
+ nolutram = true;
+ continue;
+ }
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
@@ -144,10 +160,14 @@ struct SynthGowinPass : public ScriptPass
nowidelut = true;
continue;
}
- //if (args[argidx] == "-abc9") {
- // abc9 = true;
- // continue;
- //}
+ if (args[argidx] == "-noalu") {
+ noalu = true;
+ continue;
+ }
+ if (args[argidx] == "-abc9") {
+ abc9 = true;
+ continue;
+ }
if (args[argidx] == "-noiopads") {
noiopads = true;
continue;
@@ -171,7 +191,7 @@ struct SynthGowinPass : public ScriptPass
{
if (check_label("begin"))
{
- run("read_verilog -lib +/gowin/cells_sim.v");
+ run("read_verilog -specify -lib +/gowin/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
@@ -198,7 +218,7 @@ struct SynthGowinPass : public ScriptPass
{
run("memory_bram -rules +/gowin/lutrams.txt");
run("techmap -map +/gowin/lutrams_map.v");
- run("determine_init");
+ run("setundef -params -zero t:RAM16S4");
}
if (check_label("map_ffram"))
@@ -210,19 +230,26 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_gates"))
{
- run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
+ if (noalu) {
+ run("techmap -map +/techmap.v");
+ } else {
+ run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
+ }
run("opt -fast");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
- run("splitnets");
+ if (!noiopads || help_mode)
+ run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
+ "-toutpad TBUF ~OEN:I:O -tinoutpad IOBUF ~OEN:O:I:IO", "(unless -noiopads)");
}
if (check_label("map_ffs"))
{
- run("dff2dffs -match-init");
run("opt_clean");
- if (!nodffe)
- run("dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*");
+ if (nodffe)
+ run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFF_?P?_ r -cell $_DFF_?P?_ r");
+ else
+ run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r");
run("techmap -map +/gowin/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");
@@ -230,13 +257,15 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_luts"))
{
- /*if (nowidelut && abc9) {
- run("abc9 -lut 4");
- } else*/ if (nowidelut && !abc9) {
+ if (nowidelut && abc9) {
+ run("read_verilog -icells -lib -specify +/abc9_model.v");
+ run("abc9 -maxlut 4 -W 500");
+ } else if (nowidelut && !abc9) {
run("abc -lut 4");
- } else /*if (!nowidelut && abc9) {
- run("abc9 -lut 4:8");
- } else*/ if (!nowidelut && !abc9) {
+ } else if (!nowidelut && abc9) {
+ run("read_verilog -icells -lib -specify +/abc9_model.v");
+ run("abc9 -maxlut 8 -W 500");
+ } else if (!nowidelut && !abc9) {
run("abc -lut 4:8");
}
run("clean");
@@ -248,10 +277,10 @@ struct SynthGowinPass : public ScriptPass
run("opt_lut_ins -tech gowin");
run("setundef -undriven -params -zero");
run("hilomap -singleton -hicell VCC V -locell GND G");
- if (!noiopads || help_mode)
- run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
- "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)");
+ if (!vout_file.empty() || help_mode) // vendor output requires 1-bit wires
+ run("splitnets -ports", "(only if -vout used)");
run("clean");
+ run("autoname");
}
if (check_label("check"))
@@ -259,13 +288,17 @@ struct SynthGowinPass : public ScriptPass
run("hierarchy -check");
run("stat");
run("check -noinit");
+ run("blackbox =A:whitebox");
}
if (check_label("vout"))
{
if (!vout_file.empty() || help_mode)
- run(stringf("write_verilog -decimal -attr2comment -defparam -renameprefix gen %s",
+ run(stringf("write_verilog -simple-lhs -decimal -attr2comment -defparam -renameprefix gen %s",
help_mode ? "<file-name>" : vout_file.c_str()));
+ if (!json_file.empty() || help_mode)
+ run(stringf("write_json %s",
+ help_mode ? "<file-name>" : json_file.c_str()));
}
}
} SynthGowinPass;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 00:01:54 +0000