diff options
Diffstat (limited to 'techlibs/gowin')
| -rw-r--r-- | techlibs/gowin/cells_sim.v | 45 | ||||
| -rw-r--r-- | techlibs/gowin/synth_gowin.cc | 35 |
2 files changed, 77 insertions, 3 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 47ece84df..509bf3ef2 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -821,3 +821,48 @@ endspecify endmodule +(* blackbox *) +module rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P); +input CLKIN; +input CLKFB; +input RESET; +input RESET_P; +input [5:0] FBDSEL; +input [5:0] IDSEL; +input [5:0] ODSEL; +input [3:0] PSDA,FDLY; +input [3:0] DUTYDA; + +output CLKOUT; +output LOCK; +output CLKOUTP; +output CLKOUTD; +output CLKOUTD3; + +parameter FCLKIN = "100.0"; // frequency of CLKIN +parameter DYN_IDIV_SEL= "false"; // true:IDSEL, false:IDIV_SEL +parameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64 +parameter DYN_FBDIV_SEL= "false"; // true:FBDSEL, false:FBDIV_SEL +parameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64 +parameter DYN_ODIV_SEL= "false"; // true:ODSEL, false:ODIV_SEL +parameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128 + +parameter PSDA_SEL= "0000"; +parameter DYN_DA_EN = "false"; // true:PSDA or DUTYDA or FDA, false: DA_SEL +parameter DUTYDA_SEL= "1000"; + +parameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only +parameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only +parameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4 +parameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2 + +parameter CLKFB_SEL = "internal"; // "internal", "external" +parameter CLKOUT_BYPASS = "false"; // "true", "false" +parameter CLKOUTP_BYPASS = "false"; // "true", "false" +parameter CLKOUTD_BYPASS = "false"; // "true", "false" +parameter DYN_SDIV_SEL = 2; // 2~128, only even numbers +parameter CLKOUTD_SRC = "CLKOUT"; // CLKOUT, CLKOUTP +parameter CLKOUTD3_SRC = "CLKOUT"; // CLKOUT, CLKOUTP +parameter DEVICE = "GW1N-1"; // "GW1N-1", "GW1N-4", "GW1N-9", "GW1NR-4", "GW1NR-9", "GW1N-4B", "GW1NR-4B", "GW1NS-2", "GW1NS-2C", "GW1NZ-1", "GW1NSR-2", "GW1NSR-2C", "GW1N-1S", "GW1NSE-2C", "GW1NRF-4B", "GW1N-9C", "GW1NR-9C", "GW1N-4C", "GW1NR-4C" + +endmodule diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 4d1e968ae..5bf0894da 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -44,6 +44,11 @@ struct SynthGowinPass : public ScriptPass log(" write the design to the specified Verilog netlist file. writing of an\n"); log(" output file is omitted if this parameter is not specified.\n"); log("\n"); + log(" -json <file>\n"); + log(" write the design to the specified JSON netlist file. writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); + log(" This disables features not yet supported by nexpnr-gowin.\n"); + log("\n"); log(" -run <from_label>:<to_label>\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -70,6 +75,9 @@ struct SynthGowinPass : public ScriptPass log(" -noiopads\n"); log(" do not emit IOB at top level ports\n"); log("\n"); + log(" -noalu\n"); + log(" do not use ALU cells\n"); + log("\n"); log(" -abc9\n"); log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); @@ -79,13 +87,14 @@ struct SynthGowinPass : public ScriptPass log("\n"); } - string top_opt, vout_file; - bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads; + string top_opt, vout_file, json_file; + bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads, noalu; void clear_flags() override { top_opt = "-auto-top"; vout_file = ""; + json_file = ""; retime = false; flatten = true; nobram = false; @@ -94,6 +103,7 @@ struct SynthGowinPass : public ScriptPass nowidelut = false; abc9 = false; noiopads = false; + noalu = false; } void execute(std::vector<std::string> args, RTLIL::Design *design) override @@ -112,6 +122,14 @@ struct SynthGowinPass : public ScriptPass vout_file = args[++argidx]; continue; } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + nobram = true; + nolutram = true; + nowidelut = true; + noalu = true; + continue; + } if (args[argidx] == "-run" && argidx+1 < args.size()) { size_t pos = args[argidx+1].find(':'); if (pos == std::string::npos) @@ -144,6 +162,10 @@ struct SynthGowinPass : public ScriptPass nowidelut = true; continue; } + if (args[argidx] == "-noalu") { + noalu = true; + continue; + } if (args[argidx] == "-abc9") { abc9 = true; continue; @@ -210,7 +232,11 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_gates")) { - run("techmap -map +/techmap.v -map +/gowin/arith_map.v"); + if (noalu) { + run("techmap -map +/techmap.v"); + } else { + run("techmap -map +/techmap.v -map +/gowin/arith_map.v"); + } run("opt -fast"); if (retime || help_mode) run("abc -dff -D 1", "(only if -retime)"); @@ -270,6 +296,9 @@ struct SynthGowinPass : public ScriptPass if (!vout_file.empty() || help_mode) run(stringf("write_verilog -decimal -attr2comment -defparam -renameprefix gen %s", help_mode ? "<file-name>" : vout_file.c_str())); + if (!json_file.empty() || help_mode) + run(stringf("write_json %s", + help_mode ? "<file-name>" : json_file.c_str())); } } } SynthGowinPass; |