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-rw-r--r--techlibs/gowin/Makefile.inc1
-rw-r--r--techlibs/gowin/cells_map.v185
-rw-r--r--techlibs/gowin/cells_sim.v404
-rw-r--r--techlibs/gowin/determine_init.cc72
-rw-r--r--techlibs/gowin/synth_gowin.cc48
5 files changed, 442 insertions, 268 deletions
diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc
index 0756e3bcf..e6a6be970 100644
--- a/techlibs/gowin/Makefile.inc
+++ b/techlibs/gowin/Makefile.inc
@@ -1,6 +1,5 @@
OBJS += techlibs/gowin/synth_gowin.o
-OBJS += techlibs/gowin/determine_init.o
GENFILES += techlibs/gowin/bram_init_16.vh
diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index b44350616..851ef20b2 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -3,228 +3,123 @@
//value regardless. The parameter is ignored.
// DFFN D Flip-Flop with Negative-Edge Clock
-module \$_DFF_N_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q);
- generate
- if (_TECHMAP_WIREINIT_Q_ === 1'b1)
- DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0));
- else
- DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
- endgenerate
+module \$_DFF_N_ (input D, C, output Q);
+ DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFF D Flip-Flop
-module \$_DFF_P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q);
- generate
- if (_TECHMAP_WIREINIT_Q_ === 1'b1)
- DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0));
- else
- DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
- endgenerate
+module \$_DFF_P_ (input D, C, output Q);
+ DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFE D Flip-Flop with Clock Enable
-module \$_DFFE_PP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
- generate
- if (_TECHMAP_WIREINIT_Q_ === 1'b1)
- DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0));
- else
- DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
- endgenerate
- wire _TECHMAP_REMOVEINIT_Q_ = 1;
-endmodule
-
-module \$_DFFE_PN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
- generate
- if (_TECHMAP_WIREINIT_Q_ === 1'b1)
- DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0));
- else
- DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E));
- endgenerate
+module \$_DFFE_PP_ (input D, C, E, output Q);
+ DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable
-module \$_DFFE_NP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
- generate
- if (_TECHMAP_WIREINIT_Q_ === 1'b1)
- DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0));
- else
- DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
- endgenerate
- wire _TECHMAP_REMOVEINIT_Q_ = 1;
-endmodule
-
-module \$_DFFE_NN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
- generate
- if (_TECHMAP_WIREINIT_Q_ === 1'b1)
- DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0));
- else
- DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E));
- endgenerate
+module \$_DFFE_NP_ (input D, C, E, output Q);
+ DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFR D Flip-Flop with Synchronous Reset
-module \$__DFFS_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
- DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-
-module \$__DFFS_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_PP0_ (input D, C, R, output Q);
DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset
-module \$__DFFS_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
- DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$__DFFS_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_NP0_ (input D, C, R, output Q);
DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset
-module \$__DFFSE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
- DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$__DFFSE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_PP0P_ (input D, C, R, E, output Q);
DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
-module \$__DFFSE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
- DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$__DFFSE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_NP0P_ (input D, C, R, E, output Q);
DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFS D Flip-Flop with Synchronous Set
-module \$__DFFS_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
- DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$__DFFS_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_PP1_ (input D, C, R, output Q);
DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set
-module \$__DFFS_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
- DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$__DFFS_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_NP1_ (input D, C, R, output Q);
DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFSE D Flip-Flop with Clock Enable and Synchronous Set
-module \$__DFFSE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
- DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$__DFFSE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_PP1P_ (input D, C, R, E, output Q);
DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
-module \$__DFFSE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
- DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$__DFFSE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_NP1P_ (input D, C, R, E, output Q);
DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFP D Flip-Flop with Asynchronous Preset
-module \$_DFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_DFF_PP1_ (input D, C, R, output Q);
DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$_DFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
- DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
-module \$_DFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_DFF_NP1_ (input D, C, R, output Q);
DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$_DFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
- DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFC D Flip-Flop with Asynchronous Clear
-module \$_DFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_DFF_PP0_ (input D, C, R, output Q);
DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$_DFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
- DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
-module \$_DFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_DFF_NP0_ (input D, C, R, output Q);
DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$_DFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
- DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset
-module \$__DFFE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_PP1P_ (input D, C, R, E, output Q);
DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$__DFFE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
- DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
-module \$__DFFE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_NP1P_ (input D, C, R, E, output Q);
DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
-endmodule
-module \$__DFFE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
- DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear
-module \$__DFFE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_PP0P_ (input D, C, R, E, output Q);
DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$__DFFE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
- DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
-module \$__DFFE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_NP0P_ (input D, C, R, E, output Q);
DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
-endmodule
-module \$__DFFE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
- DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
- wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index a67855dab..509bf3ef2 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -1,33 +1,112 @@
+(* abc9_lut=1 *)
module LUT1(output F, input I0);
parameter [1:0] INIT = 0;
+ specify
+ (I0 => F) = (555, 902);
+ endspecify
assign F = I0 ? INIT[1] : INIT[0];
endmodule
+(* abc9_lut=1 *)
module LUT2(output F, input I0, I1);
parameter [3:0] INIT = 0;
+ specify
+ (I0 => F) = (867, 1184);
+ (I1 => F) = (555, 902);
+ endspecify
wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
+(* abc9_lut=1 *)
module LUT3(output F, input I0, I1, I2);
parameter [7:0] INIT = 0;
+ specify
+ (I0 => F) = (1054, 1486);
+ (I1 => F) = (867, 1184);
+ (I2 => F) = (555, 902);
+ endspecify
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
+(* abc9_lut=1 *)
module LUT4(output F, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
+ specify
+ (I0 => F) = (1054, 1486);
+ (I1 => F) = (1053, 1583);
+ (I2 => F) = (867, 1184);
+ (I3 => F) = (555, 902);
+ endspecify
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
+(* abc9_lut=2 *)
+module __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);
+ specify
+ (I0 => F) = (1187, 1638);
+ (I1 => F) = (1184, 1638);
+ (I2 => F) = (995, 1371);
+ (I3 => F) = (808, 1116);
+ (M0 => F) = (486, 680);
+ endspecify
+endmodule
+
+(* abc9_lut=4 *)
+module __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);
+ specify
+ (I0 => F) = (1187 + 136, 1638 + 255);
+ (I1 => F) = (1184 + 136, 1638 + 255);
+ (I2 => F) = (995 + 136, 1371 + 255);
+ (I3 => F) = (808 + 136, 1116 + 255);
+ (M0 => F) = (486 + 136, 680 + 255);
+ (M1 => F) = (478, 723);
+ endspecify
+endmodule
+
+(* abc9_lut=8 *)
+module __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);
+ specify
+ (I0 => F) = (1187 + 136 + 136, 1638 + 255 + 255);
+ (I1 => F) = (1184 + 136 + 136, 1638 + 255 + 255);
+ (I2 => F) = (995 + 136 + 136, 1371 + 255 + 255);
+ (I3 => F) = (808 + 136 + 136, 1116 + 255 + 255);
+ (M0 => F) = (486 + 136 + 136, 680 + 255 + 255);
+ (M1 => F) = (478 + 136, 723 + 255);
+ (M2 => F) = (478, 723);
+ endspecify
+endmodule
+
+(* abc9_lut=16 *)
+module __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);
+ specify
+ (I0 => F) = (1187 + 136 + 136 + 136, 1638 + 255 + 255 + 255);
+ (I1 => F) = (1184 + 136 + 136 + 136, 1638 + 255 + 255 + 255);
+ (I2 => F) = (995 + 136 + 136 + 136, 1371 + 255 + 255 + 255);
+ (I3 => F) = (808 + 136 + 136 + 136, 1116 + 255 + 255 + 255);
+ (M0 => F) = (486 + 136 + 136 + 136, 680 + 255 + 255 + 255);
+ (M1 => F) = (478 + 136 + 136, 723 + 255 + 255);
+ (M2 => F) = (478 + 136, 723 + 255);
+ (M3 => F) = (478, 723);
+ endspecify
+ endmodule
+
module MUX2 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
+
+ specify
+ (I0 => O) = (141, 160);
+ (I1 => O) = (141, 160);
+ (S0 => O) = (486, 680);
+ endspecify
+
assign O = S0 ? I1 : I0;
endmodule
@@ -35,6 +114,13 @@ module MUX2_LUT5 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
+
+ specify
+ (I0 => O) = (141, 160);
+ (I1 => O) = (141, 160);
+ (S0 => O) = (486, 680);
+ endspecify
+
MUX2 mux2_lut5 (O, I0, I1, S0);
endmodule
@@ -42,6 +128,13 @@ module MUX2_LUT6 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
+
+ specify
+ (I0 => O) = (136, 255);
+ (I1 => O) = (136, 255);
+ (S0 => O) = (478, 723);
+ endspecify
+
MUX2 mux2_lut6 (O, I0, I1, S0);
endmodule
@@ -49,6 +142,13 @@ module MUX2_LUT7 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
+
+ specify
+ (I0 => O) = (136, 255);
+ (I1 => O) = (136, 255);
+ (S0 => O) = (478, 723);
+ endspecify
+
MUX2 mux2_lut7 (O, I0, I1, S0);
endmodule
@@ -56,29 +156,58 @@ module MUX2_LUT8 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
+
+ specify
+ (I0 => O) = (136, 255);
+ (I1 => O) = (136, 255);
+ (S0 => O) = (478, 723);
+ endspecify
+
MUX2 mux2_lut8 (O, I0, I1, S0);
endmodule
+(* abc9_flop, lib_whitebox *)
module DFF (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
+
+ specify
+ (posedge CLK => (Q : D)) = (480, 660);
+ $setup(D, posedge CLK, 576);
+ endspecify
+
always @(posedge CLK)
Q <= D;
endmodule
+(* abc9_flop, lib_whitebox *)
module DFFE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
+
+ specify
+ if (CE) (posedge CLK => (Q : D)) = (480, 660);
+ $setup(D, posedge CLK &&& CE, 576);
+ $setup(CE, posedge CLK, 63);
+ endspecify
+
always @(posedge CLK) begin
if (CE)
Q <= D;
end
endmodule // DFFE (positive clock edge; clock enable)
-
+(* abc9_box, lib_whitebox *)
module DFFS (output reg Q, input D, CLK, SET);
- parameter [0:0] INIT = 1'b0;
+ parameter [0:0] INIT = 1'b1;
initial Q = INIT;
+
+ specify
+ (posedge CLK => (Q : D)) = (480, 660);
+ $setup(D, posedge CLK, 576);
+ $setup(SET, posedge CLK, 63);
+ endspecify
+
always @(posedge CLK) begin
if (SET)
Q <= 1'b1;
@@ -87,10 +216,18 @@ module DFFS (output reg Q, input D, CLK, SET);
end
endmodule // DFFS (positive clock edge; synchronous set)
-
+(* abc9_box, lib_whitebox *)
module DFFSE (output reg Q, input D, CLK, CE, SET);
- parameter [0:0] INIT = 1'b0;
+ parameter [0:0] INIT = 1'b1;
initial Q = INIT;
+
+ specify
+ if (CE) (posedge CLK => (Q : D)) = (480, 660);
+ $setup(D, posedge CLK &&& CE, 576);
+ $setup(CE, posedge CLK, 63);
+ $setup(SET, posedge CLK, 63);
+ endspecify
+
always @(posedge CLK) begin
if (SET)
Q <= 1'b1;
@@ -99,10 +236,17 @@ module DFFSE (output reg Q, input D, CLK, CE, SET);
end
endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)
-
+(* abc9_flop, lib_whitebox *)
module DFFR (output reg Q, input D, CLK, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
+
+ specify
+ (posedge CLK => (Q : D)) = (480, 660);
+ $setup(D, posedge CLK, 576);
+ $setup(RESET, posedge CLK, 63);
+ endspecify
+
always @(posedge CLK) begin
if (RESET)
Q <= 1'b0;
@@ -111,10 +255,18 @@ module DFFR (output reg Q, input D, CLK, RESET);
end
endmodule // DFFR (positive clock edge; synchronous reset)
-
+(* abc9_flop, lib_whitebox *)
module DFFRE (output reg Q, input D, CLK, CE, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
+
+ specify
+ if (CE) (posedge CLK => (Q : D)) = (480, 660);
+ $setup(D, posedge CLK &&& CE, 576);
+ $setup(CE, posedge CLK, 63);
+ $setup(RESET, posedge CLK, 63);
+ endspecify
+
always @(posedge CLK) begin
if (RESET)
Q <= 1'b0;
@@ -123,10 +275,17 @@ module DFFRE (output reg Q, input D, CLK, CE, RESET);
end
endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)
-
+(* abc9_box, lib_whitebox *)
module DFFP (output reg Q, input D, CLK, PRESET);
- parameter [0:0] INIT = 1'b0;
+ parameter [0:0] INIT = 1'b1;
initial Q = INIT;
+
+ specify
+ (posedge CLK => (Q : D)) = (480, 660);
+ (posedge PRESET => (Q : 1'b1)) = (1800, 2679);
+ $setup(D, posedge CLK, 576);
+ endspecify
+
always @(posedge CLK or posedge PRESET) begin
if(PRESET)
Q <= 1'b1;
@@ -135,10 +294,18 @@ module DFFP (output reg Q, input D, CLK, PRESET);
end
endmodule // DFFP (positive clock edge; asynchronous preset)
-
+(* abc9_box, lib_whitebox *)
module DFFPE (output reg Q, input D, CLK, CE, PRESET);
- parameter [0:0] INIT = 1'b0;
+ parameter [0:0] INIT = 1'b1;
initial Q = INIT;
+
+ specify
+ if (CE) (posedge CLK => (Q : D)) = (480, 660);
+ (posedge PRESET => (Q : 1'b1)) = (1800, 2679);
+ $setup(D, posedge CLK &&& CE, 576);
+ $setup(CE, posedge CLK, 63);
+ endspecify
+
always @(posedge CLK or posedge PRESET) begin
if(PRESET)
Q <= 1'b1;
@@ -147,10 +314,17 @@ module DFFPE (output reg Q, input D, CLK, CE, PRESET);
end
endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)
-
+(* abc9_box, lib_whitebox *)
module DFFC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
+
+ specify
+ (posedge CLK => (Q : D)) = (480, 660);
+ (posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
+ $setup(D, posedge CLK, 576);
+ endspecify
+
always @(posedge CLK or posedge CLEAR) begin
if(CLEAR)
Q <= 1'b0;
@@ -159,10 +333,18 @@ module DFFC (output reg Q, input D, CLK, CLEAR);
end
endmodule // DFFC (positive clock edge; asynchronous clear)
-
+(* abc9_box, lib_whitebox *)
module DFFCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
+
+ specify
+ if (CE) (posedge CLK => (Q : D)) = (480, 660);
+ (posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
+ $setup(D, posedge CLK &&& CE, 576);
+ $setup(CE, posedge CLK, 63);
+ endspecify
+
always @(posedge CLK or posedge CLEAR) begin
if(CLEAR)
Q <= 1'b0;
@@ -171,27 +353,48 @@ module DFFCE (output reg Q, input D, CLK, CE, CLEAR);
end
endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
-
+(* abc9_flop, lib_whitebox *)
module DFFN (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
+
+ specify
+ (negedge CLK => (Q : D)) = (480, 660);
+ $setup(D, negedge CLK, 576);
+ endspecify
+
always @(negedge CLK)
Q <= D;
endmodule
+(* abc9_flop, lib_whitebox *)
module DFFNE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
+
+ specify
+ if (CE) (negedge CLK => (Q : D)) = (480, 660);
+ $setup(D, negedge CLK &&& CE, 576);
+ $setup(CE, negedge CLK, 63);
+ endspecify
+
always @(negedge CLK) begin
if (CE)
Q <= D;
end
endmodule // DFFNE (negative clock edge; clock enable)
-
+(* abc9_box, lib_whitebox *)
module DFFNS (output reg Q, input D, CLK, SET);
- parameter [0:0] INIT = 1'b0;
+ parameter [0:0] INIT = 1'b1;
initial Q = INIT;
+
+ specify
+ (negedge CLK => (Q : D)) = (480, 660);
+ $setup(D, negedge CLK, 576);
+ $setup(SET, negedge CLK, 63);
+ endspecify
+
always @(negedge CLK) begin
if (SET)
Q <= 1'b1;
@@ -200,10 +403,18 @@ module DFFNS (output reg Q, input D, CLK, SET);
end
endmodule // DFFNS (negative clock edge; synchronous set)
-
+(* abc9_box, lib_whitebox *)
module DFFNSE (output reg Q, input D, CLK, CE, SET);
- parameter [0:0] INIT = 1'b0;
+ parameter [0:0] INIT = 1'b1;
initial Q = INIT;
+
+ specify
+ if (CE) (negedge CLK => (Q : D)) = (480, 660);
+ $setup(D, negedge CLK &&& CE, 576);
+ $setup(CE, negedge CLK, 63);
+ $setup(SET, negedge CLK, 63);
+ endspecify
+
always @(negedge CLK) begin
if (SET)
Q <= 1'b1;
@@ -212,10 +423,17 @@ module DFFNSE (output reg Q, input D, CLK, CE, SET);
end
endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)
-
+(* abc9_flop, lib_whitebox *)
module DFFNR (output reg Q, input D, CLK, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
+
+ specify
+ (negedge CLK => (Q : D)) = (480, 660);
+ $setup(D, negedge CLK, 576);
+ $setup(RESET, negedge CLK, 63);
+ endspecify
+
always @(negedge CLK) begin
if (RESET)
Q <= 1'b0;
@@ -224,10 +442,18 @@ module DFFNR (output reg Q, input D, CLK, RESET);
end
endmodule // DFFNR (negative clock edge; synchronous reset)
-
+(* abc9_flop, lib_whitebox *)
module DFFNRE (output reg Q, input D, CLK, CE, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
+
+ specify
+ if (CE) (negedge CLK => (Q : D)) = (480, 660);
+ $setup(D, negedge CLK &&& CE, 576);
+ $setup(CE, negedge CLK, 63);
+ $setup(RESET, negedge CLK, 63);
+ endspecify
+
always @(negedge CLK) begin
if (RESET)
Q <= 1'b0;
@@ -236,10 +462,17 @@ module DFFNRE (output reg Q, input D, CLK, CE, RESET);
end
endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)
-
+(* abc9_box, lib_whitebox *)
module DFFNP (output reg Q, input D, CLK, PRESET);
- parameter [0:0] INIT = 1'b0;
+ parameter [0:0] INIT = 1'b1;
initial Q = INIT;
+
+ specify
+ (negedge CLK => (Q : D)) = (480, 660);
+ (posedge PRESET => (Q : 1'b1)) = (1800, 2679);
+ $setup(D, negedge CLK, 576);
+ endspecify
+
always @(negedge CLK or posedge PRESET) begin
if(PRESET)
Q <= 1'b1;
@@ -248,10 +481,18 @@ module DFFNP (output reg Q, input D, CLK, PRESET);
end
endmodule // DFFNP (negative clock edge; asynchronous preset)
-
+(* abc9_box, lib_whitebox *)
module DFFNPE (output reg Q, input D, CLK, CE, PRESET);
- parameter [0:0] INIT = 1'b0;
+ parameter [0:0] INIT = 1'b1;
initial Q = INIT;
+
+ specify
+ if (CE) (negedge CLK => (Q : D)) = (480, 660);
+ (posedge PRESET => (Q : 1'b1)) = (1800, 2679);
+ $setup(D, negedge CLK &&& CE, 576);
+ $setup(CE, negedge CLK, 63);
+ endspecify
+
always @(negedge CLK or posedge PRESET) begin
if(PRESET)
Q <= 1'b1;
@@ -260,10 +501,17 @@ module DFFNPE (output reg Q, input D, CLK, CE, PRESET);
end
endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)
-
+(* abc9_box, lib_whitebox *)
module DFFNC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
+
+ specify
+ (negedge CLK => (Q : D)) = (480, 660);
+ (posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
+ $setup(D, negedge CLK, 576);
+ endspecify
+
always @(negedge CLK or posedge CLEAR) begin
if(CLEAR)
Q <= 1'b0;
@@ -272,10 +520,18 @@ module DFFNC (output reg Q, input D, CLK, CLEAR);
end
endmodule // DFFNC (negative clock edge; asynchronous clear)
-
+(* abc9_box, lib_whitebox *)
module DFFNCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
+
+ specify
+ if (CE) (negedge CLK => (Q : D)) = (480, 660);
+ (posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
+ $setup(D, negedge CLK &&& CE, 576);
+ $setup(CE, negedge CLK, 63);
+ endspecify
+
always @(negedge CLK or posedge CLEAR) begin
if(CLEAR)
Q <= 1'b0;
@@ -294,11 +550,23 @@ module GND(output G);
assign G = 0;
endmodule
+(* abc9_box *)
module IBUF(output O, input I);
+
+ specify
+ (I => O) = 0;
+ endspecify
+
assign O = I;
endmodule
+(* abc9_box *)
module OBUF(output O, input I);
+
+ specify
+ (I => O) = 0;
+ endspecify
+
assign O = I;
endmodule
@@ -320,14 +588,15 @@ module GSR (input GSRI);
wire GSRO = GSRI;
endmodule
+(* abc9_box, lib_whitebox *)
module ALU (SUM, COUT, I0, I1, I3, CIN);
input I0;
input I1;
input I3;
-input CIN;
+(* abc9_carry *) input CIN;
output SUM;
-output COUT;
+(* abc9_carry *) output COUT;
localparam ADD = 0;
localparam SUB = 1;
@@ -344,6 +613,17 @@ parameter ALU_MODE = 0;
reg S, C;
+specify
+ (I0 => SUM) = (1043, 1432);
+ (I1 => SUM) = (775, 1049);
+ (I3 => SUM) = (751, 1010);
+ (CIN => SUM) = (694, 811);
+ (I0 => COUT) = (1010, 1380);
+ (I1 => COUT) = (1021, 1505);
+ (I3 => COUT) = (483, 792);
+ (CIN => COUT) = (49, 82);
+endspecify
+
assign SUM = S ^ CIN;
assign COUT = S? CIN : C;
@@ -394,7 +674,6 @@ end
endmodule
-
module RAM16S4 (DO, DI, AD, WRE, CLK);
parameter WIDTH = 4;
parameter INIT_0 = 16'h0000;
@@ -408,6 +687,14 @@ module RAM16S4 (DO, DI, AD, WRE, CLK);
input CLK;
input WRE;
+ specify
+ (AD => DO) = (270, 405);
+ $setup(DI, posedge CLK, 62);
+ $setup(WRE, posedge CLK, 62);
+ $setup(AD, posedge CLK, 62);
+ (posedge CLK => (DO : {WIDTH{1'bx}})) = (474, 565);
+ endspecify
+
reg [15:0] mem0, mem1, mem2, mem3;
initial begin
@@ -516,5 +803,66 @@ input [31:0] DI;
input [2:0] BLKSEL;
output [31:0] DO;
+specify
+ (posedge CLKB => (DO : DI)) = (419, 493);
+ $setup(RESETA, posedge CLKA, 62);
+ $setup(RESETB, posedge CLKB, 62);
+ $setup(OCE, posedge CLKB, 62);
+ $setup(CEA, posedge CLKA, 62);
+ $setup(CEB, posedge CLKB, 62);
+ $setup(OCE, posedge CLKB, 62);
+ $setup(WREA, posedge CLKA, 62);
+ $setup(WREB, posedge CLKB, 62);
+ $setup(DI, posedge CLKA, 62);
+ $setup(ADA, posedge CLKA, 62);
+ $setup(ADB, posedge CLKB, 62);
+ $setup(BLKSEL, posedge CLKA, 62);
+endspecify
+
endmodule
+(* blackbox *)
+module rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);
+input CLKIN;
+input CLKFB;
+input RESET;
+input RESET_P;
+input [5:0] FBDSEL;
+input [5:0] IDSEL;
+input [5:0] ODSEL;
+input [3:0] PSDA,FDLY;
+input [3:0] DUTYDA;
+
+output CLKOUT;
+output LOCK;
+output CLKOUTP;
+output CLKOUTD;
+output CLKOUTD3;
+
+parameter FCLKIN = "100.0"; // frequency of CLKIN
+parameter DYN_IDIV_SEL= "false"; // true:IDSEL, false:IDIV_SEL
+parameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64
+parameter DYN_FBDIV_SEL= "false"; // true:FBDSEL, false:FBDIV_SEL
+parameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64
+parameter DYN_ODIV_SEL= "false"; // true:ODSEL, false:ODIV_SEL
+parameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128
+
+parameter PSDA_SEL= "0000";
+parameter DYN_DA_EN = "false"; // true:PSDA or DUTYDA or FDA, false: DA_SEL
+parameter DUTYDA_SEL= "1000";
+
+parameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only
+parameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only
+parameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4
+parameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2
+
+parameter CLKFB_SEL = "internal"; // "internal", "external"
+parameter CLKOUT_BYPASS = "false"; // "true", "false"
+parameter CLKOUTP_BYPASS = "false"; // "true", "false"
+parameter CLKOUTD_BYPASS = "false"; // "true", "false"
+parameter DYN_SDIV_SEL = 2; // 2~128, only even numbers
+parameter CLKOUTD_SRC = "CLKOUT"; // CLKOUT, CLKOUTP
+parameter CLKOUTD3_SRC = "CLKOUT"; // CLKOUT, CLKOUTP
+parameter DEVICE = "GW1N-1"; // "GW1N-1", "GW1N-4", "GW1N-9", "GW1NR-4", "GW1NR-9", "GW1N-4B", "GW1NR-4B", "GW1NS-2", "GW1NS-2C", "GW1NZ-1", "GW1NSR-2", "GW1NSR-2C", "GW1N-1S", "GW1NSE-2C", "GW1NRF-4B", "GW1N-9C", "GW1NR-9C", "GW1N-4C", "GW1NR-4C"
+
+endmodule
diff --git a/techlibs/gowin/determine_init.cc b/techlibs/gowin/determine_init.cc
deleted file mode 100644
index 18a64e451..000000000
--- a/techlibs/gowin/determine_init.cc
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/sigtools.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-struct DetermineInitPass : public Pass {
- DetermineInitPass() : Pass("determine_init", "Determine the init value of cells") { }
- void help() YS_OVERRIDE
- {
- log("\n");
- log(" determine_init [selection]\n");
- log("\n");
- log("Determine the init value of cells that doesn't allow unknown init value.\n");
- log("\n");
- }
-
- Const determine_init(Const init)
- {
- for (int i = 0; i < GetSize(init); i++) {
- if (init[i] != State::S0 && init[i] != State::S1)
- init[i] = State::S0;
- }
-
- return init;
- }
-
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
- {
- log_header(design, "Executing DETERMINE_INIT pass (determine init value for cells).\n");
-
- extra_args(args, args.size(), design);
-
- int cnt = 0;
- for (auto module : design->selected_modules())
- {
- for (auto cell : module->selected_cells())
- {
- if (cell->type == ID(RAM16S4))
- {
- cell->setParam(ID(INIT_0), determine_init(cell->getParam(ID(INIT_0))));
- cell->setParam(ID(INIT_1), determine_init(cell->getParam(ID(INIT_1))));
- cell->setParam(ID(INIT_2), determine_init(cell->getParam(ID(INIT_2))));
- cell->setParam(ID(INIT_3), determine_init(cell->getParam(ID(INIT_3))));
- cnt++;
- }
- }
- }
- log_header(design, "Updated %d cells with determined init value.\n", cnt);
- }
-} DetermineInitPass;
-
-PRIVATE_NAMESPACE_END
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index dd965c0b8..4d1e968ae 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -29,7 +29,7 @@ struct SynthGowinPass : public ScriptPass
{
SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -69,9 +69,9 @@ struct SynthGowinPass : public ScriptPass
log("\n");
log(" -noiopads\n");
log(" do not emit IOB at top level ports\n");
- //log("\n");
- //log(" -abc9\n");
- //log(" use new ABC9 flow (EXPERIMENTAL)\n");
+ log("\n");
+ log(" -abc9\n");
+ log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@@ -82,7 +82,7 @@ struct SynthGowinPass : public ScriptPass
string top_opt, vout_file;
bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
vout_file = "";
@@ -96,7 +96,7 @@ struct SynthGowinPass : public ScriptPass
noiopads = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -144,10 +144,10 @@ struct SynthGowinPass : public ScriptPass
nowidelut = true;
continue;
}
- //if (args[argidx] == "-abc9") {
- // abc9 = true;
- // continue;
- //}
+ if (args[argidx] == "-abc9") {
+ abc9 = true;
+ continue;
+ }
if (args[argidx] == "-noiopads") {
noiopads = true;
continue;
@@ -167,11 +167,11 @@ struct SynthGowinPass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
{
- run("read_verilog -lib +/gowin/cells_sim.v");
+ run("read_verilog -specify -lib +/gowin/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
@@ -198,7 +198,7 @@ struct SynthGowinPass : public ScriptPass
{
run("memory_bram -rules +/gowin/lutrams.txt");
run("techmap -map +/gowin/lutrams_map.v");
- run("determine_init");
+ run("setundef -params -zero t:RAM16S4");
}
if (check_label("map_ffram"))
@@ -219,10 +219,11 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_ffs"))
{
- run("dff2dffs -match-init");
run("opt_clean");
- if (!nodffe)
- run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
+ if (nodffe)
+ run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFF_?P?_ r -cell $_DFF_?P?_ r");
+ else
+ run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r");
run("techmap -map +/gowin/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");
@@ -230,13 +231,15 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_luts"))
{
- /*if (nowidelut && abc9) {
- run("abc9 -lut 4");
- } else*/ if (nowidelut && !abc9) {
+ if (nowidelut && abc9) {
+ run("read_verilog -icells -lib -specify +/abc9_model.v");
+ run("abc9 -maxlut 4 -W 500");
+ } else if (nowidelut && !abc9) {
run("abc -lut 4");
- } else /*if (!nowidelut && abc9) {
- run("abc9 -lut 4:8");
- } else*/ if (!nowidelut && !abc9) {
+ } else if (!nowidelut && abc9) {
+ run("read_verilog -icells -lib -specify +/abc9_model.v");
+ run("abc9 -maxlut 8 -W 500");
+ } else if (!nowidelut && !abc9) {
run("abc -lut 4:8");
}
run("clean");
@@ -252,6 +255,7 @@ struct SynthGowinPass : public ScriptPass
run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
"-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)");
run("clean");
+ run("autoname");
}
if (check_label("check"))
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 18:55:25 +0000