diff options
Diffstat (limited to 'techlibs/ice40/brams_map.v')
| -rw-r--r-- | techlibs/ice40/brams_map.v | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v index 8c5c7e812..19a61d73b 100644 --- a/techlibs/ice40/brams_map.v +++ b/techlibs/ice40/brams_map.v @@ -90,7 +90,7 @@ module \$__ICE40_RAM4K ( .RCLKE(RCLKE), .RE (RE ), .RADDR(RADDR), - .WCLK (WCLK ), + .WCLKN(WCLK ), .WCLKE(WCLKE), .WE (WE ), .WADDR(WADDR), @@ -119,7 +119,7 @@ module \$__ICE40_RAM4K ( .INIT_F(INIT_F) ) _TECHMAP_REPLACE_ ( .RDATA(RDATA), - .RCLK (RCLK ), + .RCLKN(RCLK ), .RCLKE(RCLKE), .RE (RE ), .RADDR(RADDR), @@ -152,11 +152,11 @@ module \$__ICE40_RAM4K ( .INIT_F(INIT_F) ) _TECHMAP_REPLACE_ ( .RDATA(RDATA), - .RCLK (RCLK ), + .RCLKN(RCLK ), .RCLKE(RCLKE), .RE (RE ), .RADDR(RADDR), - .WCLK (WCLK ), + .WCLKN(WCLK ), .WCLKE(WCLKE), .WE (WE ), .WADDR(WADDR), @@ -168,7 +168,7 @@ module \$__ICE40_RAM4K ( endmodule -module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); +module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter [0:0] CLKPOL2 = 1; parameter [0:0] CLKPOL3 = 1; @@ -179,6 +179,7 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [7:0] A1ADDR; output [15:0] A1DATA; + input A1EN; input [7:0] B1ADDR; input [15:0] B1DATA; @@ -212,18 +213,18 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), - .RCLKE(1'b1), + .RCLKE(A1EN), .RE(1'b1), .WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(~B1EN), .WCLK(CLK3), - .WCLKE(1'b1), - .WE(|B1EN) + .WCLKE(|B1EN), + .WE(1'b1) ); endmodule -module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); +module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 9; parameter CFG_DBITS = 8; @@ -242,6 +243,7 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [CFG_ABITS-1:0] A1ADDR; output [CFG_DBITS-1:0] A1DATA; + input A1EN; input [CFG_ABITS-1:0] B1ADDR; input [CFG_DBITS-1:0] B1DATA; @@ -297,13 +299,13 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .RDATA(A1DATA_16), .RADDR(A1ADDR_11), .RCLK(CLK2), - .RCLKE(1'b1), + .RCLKE(A1EN), .RE(1'b1), .WDATA(B1DATA_16), .WADDR(B1ADDR_11), .WCLK(CLK3), - .WCLKE(1'b1), - .WE(|B1EN) + .WCLKE(|B1EN), + .WE(1'b1) ); endmodule |