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-rw-r--r--techlibs/ice40/cells_sim.v59
1 files changed, 33 insertions, 26 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f9945b2b5..55b4d98c9 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,6 +127,7 @@ endmodule
// SiliconBlue Logic Cells
+(* abc_box_id = 22, lib_whitebox *)
module SB_LUT4 (output O, input I0, I1, I2, I3);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -135,24 +136,29 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0];
endmodule
-module SB_CARRY (output CO, input I0, I1, CI);
+(* abc_box_id = 21, abc_carry, lib_whitebox *)
+module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
// Positive Edge SiliconBlue FF Cells
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+`ifndef _ABC
always @(posedge C)
Q <= D;
+`else
+ always @* Q <= D;
+`endif
endmodule
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
always @(posedge C)
if (E)
Q <= D;
endmodule
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
always @(posedge C)
if (R)
Q <= 0;
@@ -160,7 +166,7 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
always @(posedge C, posedge R)
if (R)
Q <= 0;
@@ -168,7 +174,7 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
always @(posedge C)
if (S)
Q <= 1;
@@ -176,7 +182,7 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
always @(posedge C, posedge S)
if (S)
Q <= 1;
@@ -184,7 +190,7 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
always @(posedge C)
if (E) begin
if (R)
@@ -194,7 +200,7 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
end
endmodule
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
always @(posedge C, posedge R)
if (R)
Q <= 0;
@@ -202,7 +208,7 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
Q <= D;
endmodule
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
always @(posedge C)
if (E) begin
if (S)
@@ -212,7 +218,7 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
end
endmodule
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
always @(posedge C, posedge S)
if (S)
Q <= 1;
@@ -222,18 +228,18 @@ endmodule
// Negative Edge SiliconBlue FF Cells
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
always @(negedge C)
Q <= D;
endmodule
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
always @(negedge C)
if (E)
Q <= D;
endmodule
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
always @(negedge C)
if (R)
Q <= 0;
@@ -241,7 +247,7 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
always @(negedge C, posedge R)
if (R)
Q <= 0;
@@ -249,7 +255,7 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
always @(negedge C)
if (S)
Q <= 1;
@@ -257,7 +263,7 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
always @(negedge C, posedge S)
if (S)
Q <= 1;
@@ -265,7 +271,7 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
always @(negedge C)
if (E) begin
if (R)
@@ -275,7 +281,7 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
end
endmodule
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
always @(negedge C, posedge R)
if (R)
Q <= 0;
@@ -283,7 +289,7 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
Q <= D;
endmodule
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
always @(negedge C)
if (E) begin
if (S)
@@ -293,7 +299,7 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
end
endmodule
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
always @(negedge C, posedge S)
if (S)
Q <= 1;
@@ -304,7 +310,7 @@ endmodule
// SiliconBlue RAM Cells
module SB_RAM40_4K (
- output [15:0] RDATA,
+ (* abc_flop_q *) output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
@@ -472,7 +478,7 @@ module SB_RAM40_4K (
endmodule
module SB_RAM40_4KNR (
- output [15:0] RDATA,
+ (* abc_flop_q *) output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
@@ -537,7 +543,7 @@ module SB_RAM40_4KNR (
endmodule
module SB_RAM40_4KNW (
- output [15:0] RDATA,
+ (* abc_flop_q *) output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLKN, WCLKE, WE,
@@ -602,7 +608,7 @@ module SB_RAM40_4KNW (
endmodule
module SB_RAM40_4KNRNW (
- output [15:0] RDATA,
+ (* abc_flop_q *) output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
input WCLKN, WCLKE, WE,
@@ -890,12 +896,13 @@ module SB_WARMBOOT (
);
endmodule
+(* nomem2reg *)
module SB_SPRAM256KA (
input [13:0] ADDRESS,
input [15:0] DATAIN,
input [3:0] MASKWREN,
input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
- output reg [15:0] DATAOUT
+ (* abc_flop_q *) output reg [15:0] DATAOUT
);
`ifndef BLACKBOX
`ifndef EQUIV
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-16 02:09:42 +0000