diff options
Diffstat (limited to 'techlibs/ice40/cells_sim.v')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index f9945b2b5..317ae2c1f 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -127,6 +127,7 @@ endmodule // SiliconBlue Logic Cells +(* abc_box_id = 2, lib_whitebox *) module SB_LUT4 (output O, input I0, I1, I2, I3); parameter [15:0] LUT_INIT = 0; wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; @@ -135,15 +136,20 @@ module SB_LUT4 (output O, input I0, I1, I2, I3); assign O = I0 ? s1[1] : s1[0]; endmodule -module SB_CARRY (output CO, input I0, I1, CI); +(* abc_box_id = 1, abc_carry, lib_whitebox *) +module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule // Positive Edge SiliconBlue FF Cells module SB_DFF (output `SB_DFF_REG, input C, D); +`ifndef _ABC always @(posedge C) Q <= D; +`else + always @* Q <= D; +`endif endmodule module SB_DFFE (output `SB_DFF_REG, input C, E, D); @@ -890,6 +896,7 @@ module SB_WARMBOOT ( ); endmodule +(* nomem2reg *) module SB_SPRAM256KA ( input [13:0] ADDRESS, input [15:0] DATAIN, |