diff options
Diffstat (limited to 'techlibs/ice40/cells_sim.v')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 17fe2ec99..6a0e3031e 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -2350,16 +2350,19 @@ module SB_SPRAM256KA ( if (off) begin DATAOUT <= 0; end else - if (CHIPSELECT && !STANDBY && !WREN) begin - DATAOUT <= mem[ADDRESS]; - end else begin - if (CHIPSELECT && !STANDBY && WREN) begin + if (STANDBY) begin + DATAOUT <= 'bx; + end else + if (CHIPSELECT) begin + if (!WREN) begin + DATAOUT <= mem[ADDRESS]; + end else begin if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0]; if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4]; if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8]; if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12]; + DATAOUT <= 'bx; end - DATAOUT <= 'bx; end end `endif @@ -2379,9 +2382,9 @@ module SB_SPRAM256KA ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167 //$setup(negedge STANDBY, posedge CLOCK, 1715); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13206 - $setup(WREN, posedge CLK, 289); + $setup(WREN, posedge CLOCK, 289); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207-L13222 - (posedge RCLK => (DATAOUT : 16'bx)) = 1821; + (posedge CLOCK => (DATAOUT : 16'bx)) = 1821; // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13223-L13238 (posedge SLEEP => (DATAOUT : 16'b0)) = 1099; endspecify |