diff options
Diffstat (limited to 'techlibs/ice40/tests/test_ffs.v')
| -rw-r--r-- | techlibs/ice40/tests/test_ffs.v | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/techlibs/ice40/tests/test_ffs.v b/techlibs/ice40/tests/test_ffs.v index 3bef59fb3..1f6883f3c 100644 --- a/techlibs/ice40/tests/test_ffs.v +++ b/techlibs/ice40/tests/test_ffs.v @@ -3,6 +3,7 @@ module test(D, C, E, R, Q); parameter [0:0] ENABLE_EN = 0; parameter [0:0] RESET_EN = 0; parameter [0:0] RESET_VAL = 0; + parameter [0:0] RESET_SYN = 0; (* gentb_clock *) input D, C, E, R; @@ -11,7 +12,7 @@ module test(D, C, E, R, Q); wire gated_reset = R & RESET_EN; wire gated_enable = E | ~ENABLE_EN; - reg posedge_q, negedge_q; + reg posedge_q, negedge_q, posedge_sq, negedge_sq; always @(posedge C, posedge gated_reset) if (gated_reset) @@ -25,5 +26,17 @@ module test(D, C, E, R, Q); else if (gated_enable) negedge_q <= D; - assign Q = CLKPOL ? posedge_q : negedge_q; + always @(posedge C) + if (gated_reset) + posedge_sq <= RESET_VAL; + else if (gated_enable) + posedge_sq <= D; + + always @(negedge C) + if (gated_reset) + negedge_sq <= RESET_VAL; + else if (gated_enable) + negedge_sq <= D; + + assign Q = RESET_SYN ? (CLKPOL ? posedge_sq : negedge_sq) : (CLKPOL ? posedge_q : negedge_q); endmodule |